targets/ac701: cleanup and make it similar to others targets.
Still supports EthernetSoC with RGMII and 1000BaseX.
This commit is contained in:
Florent Kermarrec
parent
a24bf72fc7
commit
d2ad14417a
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@ -2,16 +2,14 @@
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import argparse
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from migen import ClockDomain, Signal, Instance, Module
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from migen import *
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from litex.boards.platforms import ac701
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from litex.soc.cores.clock import S7MMCM, S7IDELAYCTRL
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from litex.soc.integration.soc_sdram import (SoCSDRAM, soc_sdram_args,
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soc_sdram_argdict)
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from litex.soc.integration.builder import (builder_args, Builder,
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builder_argdict)
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# from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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@ -19,11 +17,9 @@ from litedram.phy import s7ddrphy
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus
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from liteeth.core.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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@ -31,40 +27,33 @@ class _CRG(Module):
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk1x = ClockDomain()
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self.clock_domains.cd_clk2x = ClockDomain()
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self.clk125 = Signal()
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clk125_ds = platform.request("gtp_refclk")
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clk125_ds.p, i_IB=clk125_ds.n,
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o_O=self.clk125)
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += platform.request("sfp_mgt_clk_sel0", 0).eq(0)
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self.comb += platform.request("sfp_mgt_clk_sel1", 0).eq(0)
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self.comb += platform.request("sfp_tx_disable_n", 0).eq(0)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(self.clk125, 125e6)
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys4x.clk.attr.add("keep")
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self.cd_sys4x_dqs.clk.attr.add("keep")
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90.0)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk1x, 100e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"ddrphy": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, clk_freq=125e6, **kwargs):
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platform = ac701.Platform(programmer='xc3sprog')
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sys_clk_freq = int(clk_freq)
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def __init__(self, **kwargs):
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platform = ac701.Platform()
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sys_clk_freq = int(100e6)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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@ -73,113 +62,78 @@ class BaseSoC(SoCSDRAM):
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
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sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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class Debug(Module, AutoCSR):
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def __init__(self, lock, tx_init_done, test):
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self.foo_counter = CSRStatus(26)
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self.lock = CSRStatus(1)
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self.tx_init_done = CSRStatus(1)
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self.test = CSRStatus(1)
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counter = Signal(26)
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self.sync.eth_tx += [counter.eq(counter + 1),
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self.foo_counter.status.eq(counter)]
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self.comb += [
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self.tx_init_done.status.eq(tx_init_done),
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self.lock.status.eq(lock),
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self.test.status.eq(test)
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]
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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csr_map = {
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"ethphy": 18,
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"xadc": 19,
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"Debug": 20,
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# "ethmac": 21
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"ethmac": 19
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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# "ethmac": 3,
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"ethmac": 3,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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# "xadc": 0x30000000,
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# "ethmac": 0x30000000, # (shadow @0xb0000000)
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def setup_sfp_phy(self):
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self.create_qpll()
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self.submodules.ethphy = A7_1000BASEX(self.ethphy_qpll_channel,
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self.platform.request("sfp", 0),
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self.clk_freq)
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.txoutclk, 16.)
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self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.txoutclk, self.ethphy.rxoutclk)
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def __init__(self, phy="rgmii", **kwargs):
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assert phy in ["rgmii", "1000basex"]
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BaseSoC.__init__(self, **kwargs)
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def setup_rgmii_phy(self):
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if phy == "rgmii":
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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# self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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# self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.crg.cd_sys.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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def __init__(self, use_sfp=True, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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if use_sfp:
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self.setup_sfp_phy()
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else:
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self.setup_rgmii_phy()
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self.crg.cd_sys.clk.attr.add("keep")
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mac_address = 0x10e2d5000000
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ip_address = 0xc0a80132
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self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address,
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ip_address, self.clk_freq)
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# self.submodules.Debug = Debug(self.ethphy_qpll_channel.lock,
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# self.ethphy.tx_init.done,
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# self.ethphy.tx_init.tx_reset)
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def create_qpll(self):
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if phy == "1000basex":
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self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
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self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
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qpll_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(self.crg.clk125, qpll_settings)
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refclk125 = self.platform.request("gtp_refclk")
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refclk125_se = Signal()
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self.specials += \
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=refclk125.p,
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i_IB=refclk125.n,
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o_O=refclk125_se)
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qpll = QPLL(refclk125_se, qpll_settings)
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self.submodules += qpll
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self.ethphy_qpll_channel = qpll.channels[0]
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class EtherboneSoC(EthernetSoC):
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def __init__(self, **kwargs):
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EthernetSoC.__init__(self, **kwargs)
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234,
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mode="master")
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self.add_wb_master(self.etherbone.wishbone.bus)
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self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq)
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self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6)
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self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.txoutclk,
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self.ethphy.rxoutclk)
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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# Build --------------------------------------------------------------------------------------------
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def main():
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@ -188,9 +142,14 @@ def main():
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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parser.add_argument("--ethernet-phy", default="rgmii",
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help="select Ethernet PHY (rgmii or 1000basex)")
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args = parser.parse_args()
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cls = EtherboneSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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if args.with_ethernet:
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soc = EthernetSoC(args.ethernet_phy, **soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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