Merge pull request #1139 from tilk/jtagbone_typo

Fix typo jtabone -> jtagbone
2021-12-21 19:22:01 +01:00 · 2021-12-21 19:22:01 +01:00 · d36e1b60bd
parent 72126f90a0 92c8f7dc7c
commit d36e1b60bd
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1242,7 +1242,7 @@ class LiteXSoC(SoC):
    def add_jtagbone(self, chain=1):
        from litex.soc.cores import uart
        from litex.soc.cores.jtag import JTAGPHY
-        self.check_if_exists("jtabone")
+        self.check_if_exists("jtagbone")
        self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain)
        self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
        self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)