Merge pull request #1139 from tilk/jtagbone_typo
Fix typo jtabone -> jtagbone
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d36e1b60bd
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@ -1242,7 +1242,7 @@ class LiteXSoC(SoC):
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def add_jtagbone(self, chain=1):
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from litex.soc.cores import uart
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from litex.soc.cores.jtag import JTAGPHY
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self.check_if_exists("jtabone")
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self.check_if_exists("jtagbone")
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self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain)
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self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
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self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
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