Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)

This commit is contained in:
Florent Kermarrec 2018-01-23 10:28:16 +01:00
parent a385143779
commit d448874879
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/build/sim/core/Makefile
View File

@ -24,7 +24,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
.PHONY: sim .PHONY: sim
sim: mkdir $(OBJS_SIM) sim: mkdir $(OBJS_SIM)
verilator -Wno-fatal -O3 --cc dut.v --exe \ verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
$(SRCS_SIM_CPP) $(OBJS_SIM) \ $(SRCS_SIM_CPP) $(OBJS_SIM) \
-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
-LDFLAGS "$(LDFLAGS)" \ -LDFLAGS "$(LDFLAGS)" \

6
litex/build/sim/verilator.py
View File

@ -136,7 +136,7 @@ sudo obj_dir/Vdut
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", run=True, verbose=True, toolchain_path=None, serial="console", run=True, verbose=True,
sim_config=None): sim_config=None):
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
@ -146,9 +146,9 @@ class SimVerilatorToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_output.write("dut.v") v_output.write(build_name + ".v")
include_paths = [] include_paths = []
for source in platform.sources: for source in platform.sources: