fix README
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README
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README
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@ -11,7 +11,7 @@
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[> Intro
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[> Intro
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---------
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---------
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LiteScope small footprint and configurable embedded logic analyzer that you
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LiteScope is small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a a free, portable and flexible
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can use in your FPGA and aims to provide a a free, portable and flexible
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alternatve to vendor's solutions!
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alternatve to vendor's solutions!
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@ -35,23 +35,22 @@ by generating the verilog rtl that you will use as a standard core.
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LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
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LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
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Since LiteScope also provides an UART <--> Wishbone brige you only need 2 external
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Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
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Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
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external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
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[> Features
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[> Features
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-----------
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-----------
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- IO peek and poke with LiteScopeIO.
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- IO peek and poke with LiteScopeIO
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- Logic analyser with LiteScopeLA:
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- Logic analyser with LiteScopeLA:
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- Various triggering modules: Term, Range, Edge (add yours! :)
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- Various triggering modules: Term, Range, Edge (add yours! :)
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- Run Length Encoder to "compress" data and increase recording depth
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- Run Length Encoder to "compress" data and increase recording depth
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- Data storage in block rams
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- Data storage in block rams
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[> Possibles improvements
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[> Possibles improvements
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-------------------------
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-------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add standardized interfaces (AXI, Avalon-ST)
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- add storage in DRAM
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- add storage in DRAM
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- add storage in HDD with LiteSATA core (https://github.com/enjoy-digital/litesata)
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- add storage in HDD with LiteSATA core (to be released soon!)
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- add Ethernet Wishbone bridge
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- add Ethernet Wishbone bridge
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- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
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- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
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- ... See below Support and Consulting :)
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- ... See below Support and Consulting :)
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@ -63,7 +62,7 @@ devel [AT] lists.m-labs.hk.
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[> Getting started
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[> Getting started
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------------------
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------------------
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1. Install Python3 and Xilinx's Vivado software
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1. Install Python3 and your vendor's software
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2. Obtain Migen and install it:
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2. Obtain Migen and install it:
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git clone https://github.com/m-labs/migen
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git clone https://github.com/m-labs/migen
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@ -71,25 +70,19 @@ devel [AT] lists.m-labs.hk.
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python3 setup.py install
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python3 setup.py install
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cd ..
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cd ..
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3. Obtain Miscope and install it:
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3. Obtain MiSoC:
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git clone https://github.com/m-labs/miscope
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cd miscope
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python3 setup.py install
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cd ..
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4. Obtain MiSoC:
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git clone https://github.com/m-labs/misoc --recursive
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git clone https://github.com/m-labs/misoc --recursive
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XXX add setup.py to MiSoC for external use of misoclib?
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XXX add setup.py to MiSoC for external use of misoclib?
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5. Obtain LiteScope
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4. Obtain LiteScope
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git clone https://github.com/enjoy-digital/litescope
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git clone https://github.com/enjoy-digital/litescope
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6. Build and load test design (only for KC705 for now):
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5. Build and load test design:
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python3 make.py -s [platform] all
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python3 make.py -s [platform] all
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Supported platform are the supported platform of Mibuild:
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Supported platforms are the one altready supported by Mibuild:
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de0nano, m1, mixxeo, kc705, zedboard...
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de0nano, m1, mixxeo, kc705, zedboard...
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7. Test design:
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6. Test design:
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go to ./test directory and run:
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go to ./test directory and run:
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python3 test_io.py
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python3 test_io.py
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python3 test_la.py
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python3 test_la.py
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