bus/csr: allow specifying existing interface

This commit is contained in:
Sebastien Bourdeauducq 2012-11-17 19:44:25 +01:00
parent 86090e1cbd
commit d4baac6c0f
1 changed files with 2 additions and 2 deletions

View File

@ -17,9 +17,9 @@ class Interconnect(SimpleInterconnect):
pass pass
class Initiator(PureSimulable): class Initiator(PureSimulable):
def __init__(self, generator): def __init__(self, generator, bus=Interface()):
self.generator = generator self.generator = generator
self.bus = Interface() self.bus = bus
self.transaction = None self.transaction = None
self.done = False self.done = False