Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

mibuild: make resolve_signals public

This commit is contained in:
Sebastien Bourdeauducq 2015-02-14 03:05:07 -08:00
parent beef7425ce
commit d51d33af73
4 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
mibuild/altera_quartus.py
View File

@ -81,7 +81,7 @@ class AlteraQuartusPlatform(GenericPlatform):
self.finalize(fragment)
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self._resolve_signals(vns)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]

2
mibuild/generic_platform.py
View File

@ -240,7 +240,7 @@ class GenericPlatform:
def add_verilog_include_path(self, path):
self.verilog_include_paths.append(os.path.abspath(path))
def _resolve_signals(self, vns):
def resolve_signals(self, vns):
# resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]

4
mibuild/xilinx_ise.py
View File

@ -144,7 +144,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
if mode == "xst" or mode == "yosys":
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self._resolve_signals(vns)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
@ -162,7 +162,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
if mode == "edif" or mode == "mist":
e_src, vns = self.get_edif(fragment)
named_sc, named_pc = self._resolve_signals(vns)
named_sc, named_pc = self.resolve_signals(vns)
e_file = build_name + ".edif"
tools.write_to_file(e_file, e_src)
isemode = "edif"

2
mibuild/xilinx_vivado.py
View File

@ -103,7 +103,7 @@ class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
fragment = fragment.get_fragment()
self.finalize(fragment)
v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self._resolve_signals(vns)
named_sc, named_pc = self.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]