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build/altera: fix clock constraints 

This fixes two issues that prevented clock constraints (e.g.
"add_false_path_constraint") from working properly in Quartus.

The first fix passes the "keep" synthesis attribute through to the
generated Verilog in a way Quartus can understand.

The second fix tells Quartus to name PLL clocks according to their net
instead of the physical pin name by passing the "use_net_name" flag to
"derive_pll_clocks" in the .sdc file. Combined with the above, PLL
clocks will now be named according to the kept net.

This fix has been verified on Quartus Prime Lite 20.1.1.720.
This commit is contained in:
Thomas Watson 2022-09-30 23:33:52 -05:00
parent 3836e8a36c
commit d531a07719
1 changed files with 4 additions and 2 deletions
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6
litex/build/altera/quartus.py
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@ -22,7 +22,9 @@ from litex.build import tools
# AlteraQuartusToolchain --------------------------------------------------------------------------- # AlteraQuartusToolchain ---------------------------------------------------------------------------
class AlteraQuartusToolchain(GenericToolchain): class AlteraQuartusToolchain(GenericToolchain):
attr_translate = {} attr_translate = {
"keep": ("keep", 1),
}
def __init__(self): def __init__(self):
super().__init__() super().__init__()
@ -100,7 +102,7 @@ class AlteraQuartusToolchain(GenericToolchain):
sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period))) sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
# Enable automatical constraint generation for PLLs # Enable automatical constraint generation for PLLs
sdc.append("derive_pll_clocks") sdc.append("derive_pll_clocks -use_net_name")
# False path constraints # False path constraints
for from_, to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)): for from_, to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):