Add riscv64-none-elf triple
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@ -48,7 +48,8 @@ class BlackParrotRV64(CPU):
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name = "blackparrot"
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data_width = 64
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
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gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
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"riscv64-none-elf")
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linker_output_format = "elf64-littleriscv"
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io_regions = {0x30000000: 0x20000000} # origin, length
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@ -18,7 +18,7 @@ class Minerva(CPU):
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data_width = 32
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
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"riscv64-linux", "riscv-sifive-elf")
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"riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
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linker_output_format = "elf32-littleriscv"
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io_regions = {0x80000000: 0x80000000} # origin, length
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@ -35,7 +35,7 @@ class PicoRV32(CPU):
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data_width = 32
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
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"riscv64-linux", "riscv-sifive-elf")
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"riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
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linker_output_format = "elf32-littleriscv"
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io_regions = {0x80000000: 0x80000000} # origin, length
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@ -67,7 +67,8 @@ class RocketRV64(CPU):
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name = "rocket"
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data_width = 64
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
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gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
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"riscv64-none-elf")
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linker_output_format = "elf64-littleriscv"
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io_regions = {0x10000000: 0x70000000} # origin, length
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@ -78,7 +78,7 @@ class VexRiscv(CPU, AutoCSR):
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data_width = 32
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
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"riscv64-linux", "riscv-sifive-elf")
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"riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
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linker_output_format = "elf32-littleriscv"
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io_regions = {0x80000000: 0x80000000} # origin, length
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