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s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE

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Robert Jordens 2015-04-09 19:17:02 -06:00 committed by Sebastien Bourdeauducq
parent 603a4ef51e
commit d6c19858fa
3 changed files with 7 additions and 9 deletions
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11
misoclib/mem/sdram/phy/s6ddrphy.py
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@ -69,15 +69,18 @@ class S6DDRPHY(Module):
# sys_clk ----____----____
# phase_sel(nphases=2) 0 1 0 1 Half Rate
phase_sel = Signal(log2_int(nphases))
sys_clk_d = Signal()
phase_half = Signal.like(phase_sel)
phase_sys = Signal.like(phase_half)
sd_sys += phase_sys.eq(phase_half)
sd_sdram_half += [
If(sys_clk & ~sys_clk_d,
phase_sel.eq(0)
If(phase_half == phase_sys,
phase_sel.eq(0),
).Else(
phase_sel.eq(phase_sel+1)
),
sys_clk_d.eq(sys_clk)
phase_half.eq(phase_half+1),
]
# register dfi cmds on half_rate clk

2
targets/mlabs_video.py
View file

@ -61,8 +61,6 @@ class BaseSoC(SDRAMSoC):
platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))

3
targets/pipistrello.py
View file

@ -110,9 +110,6 @@ class BaseSoC(SDRAMSoC):
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
platform.add_platform_command("""
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size: