s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
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603a4ef51e
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@ -69,15 +69,18 @@ class S6DDRPHY(Module):
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# sys_clk ----____----____
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# sys_clk ----____----____
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# phase_sel(nphases=2) 0 1 0 1 Half Rate
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# phase_sel(nphases=2) 0 1 0 1 Half Rate
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phase_sel = Signal(log2_int(nphases))
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phase_sel = Signal(log2_int(nphases))
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sys_clk_d = Signal()
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phase_half = Signal.like(phase_sel)
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phase_sys = Signal.like(phase_half)
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sd_sys += phase_sys.eq(phase_half)
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sd_sdram_half += [
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sd_sdram_half += [
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If(sys_clk & ~sys_clk_d,
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If(phase_half == phase_sys,
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phase_sel.eq(0)
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phase_sel.eq(0),
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).Else(
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).Else(
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phase_sel.eq(phase_sel+1)
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phase_sel.eq(phase_sel+1)
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),
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),
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sys_clk_d.eq(sys_clk)
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phase_half.eq(phase_half+1),
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]
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]
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# register dfi cmds on half_rate clk
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# register dfi cmds on half_rate clk
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@ -61,8 +61,6 @@ class BaseSoC(SDRAMSoC):
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platform.add_platform_command("""
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platform.add_platform_command("""
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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""")
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platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
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platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
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@ -110,9 +110,6 @@ class BaseSoC(SDRAMSoC):
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
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]
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platform.add_platform_command("""
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PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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self.register_sdram_phy(self.ddrphy)
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self.register_sdram_phy(self.ddrphy)
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if not self.integrated_rom_size:
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if not self.integrated_rom_size:
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