integration/soc/add_etherbone: Rename ethernet parameter to with_ethmac and minor cosmetic cleanups.
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@ -1782,7 +1782,7 @@ class LiteXSoC(SoC):
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buffer_depth = 16,
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with_ip_broadcast = True,
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with_timing_constraints = True,
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ethernet = False):
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with_ethmac = False):
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# Imports
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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@ -1801,11 +1801,9 @@ class LiteXSoC(SoC):
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dw = data_width,
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with_ip_broadcast = with_ip_broadcast,
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with_sys_datapath = with_sys_datapath,
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interface = "hybrid" if ethernet else "crossbar",
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endianness = self.cpu.endianness if ethernet else "big",
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interface = {True : "hybrid", False: "crossbar"}[with_ethmac],
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endianness = {True : self.cpu.endianness, False: "big"}[with_ethmac],
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)
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if ethernet:
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ethcore.autocsr_exclude = {"mac"} # Exclude MAC here since added externally.
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if not with_sys_datapath:
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# Use PHY's eth_tx/eth_rx clock domains.
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ethcore = ClockDomainsRenamer({
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@ -1840,7 +1838,10 @@ class LiteXSoC(SoC):
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else:
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self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
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if ethernet:
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# Ethernet MAC (CPU).
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if with_ethmac:
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self.check_if_exists("ethmac")
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ethcore.autocsr_exclude = {"mac"}
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# Software Interface.
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self.ethmac = ethmac = ethcore.mac
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ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
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@ -240,7 +240,7 @@ class SimSoC(SoCCore):
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ip_address = etherbone_ip_address,
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mac_address = etherbone_mac_address,
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data_width = 8,
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ethernet = with_ethernet,
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with_ethmac = with_ethernet,
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)
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# Ethernet only ----------------------------------------------------------------------------
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elif with_ethernet:
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