build/xilinx: add disable_constraints parameter to Platform.add_ip.
When integrate .xci, we don't necessarily want to apply the default timing/loc constrants generated by Vivado but our custom ones. Setting disable_constraints to True allow disabling .xdc generated by the IP.
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@ -15,7 +15,7 @@ class XilinxPlatform(GenericPlatform):
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def __init__(self, *args, toolchain="ise", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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self.edifs = set()
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self.ips = set()
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self.ips = {}
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if toolchain == "ise":
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self.toolchain = ise.XilinxISEToolchain()
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elif toolchain == "vivado":
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@ -26,8 +26,8 @@ class XilinxPlatform(GenericPlatform):
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def add_edif(self, filename):
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self.edifs.add((os.path.abspath(filename)))
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def add_ip(self, filename):
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self.ips.add((os.path.abspath(filename)))
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def add_ip(self, filename, disable_constraints=False):
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self.ips.update({os.path.abspath(filename): disable_constraints})
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.xilinx_special_overrides)
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@ -155,7 +155,7 @@ class XilinxVivadoToolchain:
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# Add IPs
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tcl.append("\n# Add IPs\n")
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for filename in platform.ips:
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for filename, disable_constraints in platform.ips.items():
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filename_tcl = "{" + filename + "}"
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ip = os.path.splitext(os.path.basename(filename))[0]
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tcl.append("read_ip " + filename_tcl)
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@ -163,6 +163,8 @@ class XilinxVivadoToolchain:
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tcl.append("generate_target all [get_ips {}]".format(ip))
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tcl.append("synth_ip [get_ips {}] -force".format(ip))
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tcl.append("get_files -all -of_objects [get_files {}]".format(filename_tcl))
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if disable_constraints:
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tcl.append("set_property is_enabled false [get_files -of_objects [get_files {}] -filter {{FILE_TYPE == XDC}}]".format(filename_tcl))
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# Add constraints
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tcl.append("\n# Add constraints\n")
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