tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)

2019-05-09 23:33:08 +02:00 · 2019-05-09 23:33:08 +02:00 · d76a2c7db2
parent b6be534cd6
commit d76a2c7db2
1 changed files with 1 additions and 0 deletions
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
        # serial
        self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
        self.submodules.uart = uart.UART(self.uart_phy)
+        self.add_csr("uart")
        self.add_interrupt("uart")

        # sdram