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tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)

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Florent Kermarrec 2019-05-09 23:33:08 +02:00
parent b6be534cd6
commit d76a2c7db2
1 changed files with 1 additions and 0 deletions
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litex/tools/litex_sim.py
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@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
# serial # serial
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy) self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart")
self.add_interrupt("uart") self.add_interrupt("uart")
# sdram # sdram