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integration/soc: make DMA slave region cover (at least) the lower 4GB 

Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2020-08-03 14:40:45 -04:00
parent 70eae5cbf9
commit d8161e5a86
1 changed files with 1 additions and 1 deletions
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litex/soc/integration/soc.py
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@ -845,7 +845,7 @@ class SoC(Module):
data_width = self.bus.data_width, data_width = self.bus.data_width,
) )
dma_bus = wishbone.Interface(data_width=self.bus.data_width) dma_bus = wishbone.Interface(data_width=self.bus.data_width)
self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x80000000)) # FIXME: size self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus) self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus)
# Connect SoCController's reset to CPU reset # Connect SoCController's reset to CPU reset