global: more pep8
we will have to continue the work... volunteers are welcome :)
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@ -7,5 +7,5 @@ class USBBlaster(GenericProgrammer):
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needs_bitreverse = False
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def load_bitstream(self, bitstream_file, port=0):
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usb_port = "[USB-"+str(port)+"]"
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subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file])
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usb_port = "[USB-"+str(port) + "]"
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subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster" + usb_port, "-o", "p;" + bitstream_file])
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@ -5,10 +5,10 @@ from migen.genlib.record import *
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from migen.genlib.misc import chooser
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_layout = [
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("adr", "address_width", DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M)
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("adr", "address_width", DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M)
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]
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@ -6,17 +6,17 @@ from migen.genlib.fsm import FSM, NextState
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from migen.bus.transactions import *
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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("adr", 30, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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