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Convert top level comment to a docstring.

This commit is contained in:
Tim 'mithro' Ansell 2019-06-21 12:03:30 -07:00
parent 45632c66b1
commit d8ac936206
1 changed files with 7 additions and 5 deletions
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12
litex/soc/cores/up5kspram.py
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@ -1,11 +1,13 @@
from migen import *
from litex.soc.interconnect import wishbone
# ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM
# (SPRAM) primitives. Because SPRAM is much more coarse grained than Block
# RAM resources, this RAM is only minimally configurable at present (64kB or
# 128kB). Because it is single port, this module is meant to be used as the
# CPU's RAM region, leaving block RAM free for other use.
"""
ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM
(SPRAM) primitives. Because SPRAM is much more coarse grained than Block
RAM resources, this RAM is only minimally configurable at present (64kB or
128kB). Because it is single port, this module is meant to be used as the
CPU's RAM region, leaving block RAM free for other use.
"""
class Up5kSPRAM(Module):
def __init__(self, width=32, size=64*1024):