Merge pull request #1973 from motec-research/dts_schema_compliance
Dts schema compliance
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commit
d9332da433
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@ -944,6 +944,7 @@ class SoC(LiteXModule, SoCCoreCompat):
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self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC.
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self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC.
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self.constants = {}
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self.constants = {}
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self.csr_regions = {}
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self.csr_regions = {}
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self.add_constant("platform", platform.name)
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# Set Top-Level to LiteXContext.
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# Set Top-Level to LiteXContext.
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LiteXContext.top = self
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LiteXContext.top = self
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@ -247,6 +247,7 @@ class SoCCore(LiteXSoC):
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# Add Identifier.
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# Add Identifier.
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if ident != "":
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if ident != "":
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self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
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self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
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self.add_constant("identifier", ident)
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# Add UARTBone.
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# Add UARTBone.
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if with_uartbone:
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if with_uartbone:
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@ -55,14 +55,20 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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cpu_mmu = d["constants"].get("config_cpu_mmu", None)
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cpu_mmu = d["constants"].get("config_cpu_mmu", None)
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# Header ---------------------------------------------------------------------------------------
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# Header ---------------------------------------------------------------------------------------
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platform = d["constants"]["platform"]
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dts = """
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dts = """
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/dts-v1/;
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/dts-v1/;
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/ {
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/ {{
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compatible = "litex,{platform}", "litex,soc";
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model = "{identifier}";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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"""
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""".format(
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platform=platform,
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identifier=d["constants"].get("identifier", platform),
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)
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# Boot Arguments -------------------------------------------------------------------------------
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# Boot Arguments -------------------------------------------------------------------------------
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@ -161,6 +167,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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tlb_desc = ""
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tlb_desc = ""
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if "config_cpu_dtlb_size" in d["constants"]:
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if "config_cpu_dtlb_size" in d["constants"]:
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tlb_desc += """
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tlb_desc += """
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tlb-split;
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d-tlb-size = <{d_tlb_size}>;
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d-tlb-size = <{d_tlb_size}>;
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d-tlb-sets = <{d_tlb_ways}>;
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d-tlb-sets = <{d_tlb_ways}>;
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""".format(
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""".format(
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@ -181,7 +188,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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next-level-cache = <&memory>;
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next-level-cache = <&memory>;
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riscv,pmpgranularity = <4>;
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riscv,pmpgranularity = <4>;
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riscv,pmpregions = <8>;
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riscv,pmpregions = <8>;
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tlb-split;
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"""
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"""
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else:
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else:
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extra_attr = ""
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extra_attr = ""
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