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Merge pull request #1972 from motec-research/dts_all_soc_sys_clk 

tools/litex_json2dts_linux: add all soc sys_clk
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enjoy-digital 2024-05-30 09:14:11 +02:00 committed by GitHub
parent 03e0f0d9a8 8a0d50b03e
commit f8cee3836d
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1 changed files with 9 additions and 4 deletions
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13
litex/tools/litex_json2dts_linux.py
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@ -118,13 +118,18 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Clocks ------------------------------------------------------------------------------------------
dts += """
sys_clk: pll {{
for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
name = c.removesuffix("config_clock_frequency") + "sys_clk"
dts += """
{name}: clock-{freq} {{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <{sys_clk_freq}>;
clock-frequency = <{freq}>;
}};
""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
""".format(
name=name,
freq=d["constants"][c],
)
# CPU ------------------------------------------------------------------------------------------