soc/integration/soc_core: Cleanup SoCCore arguments.
This commit is contained in:
Florent Kermarrec
parent
21273ffe87
commit
d9b6d7608c
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@ -256,67 +256,49 @@ class SoCCore(LiteXSoC):
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def soc_core_args(parser):
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# Bus parameters
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parser.add_argument("--bus-standard", default="wishbone",
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help="select bus standard: {}, (default=wishbone)".format(
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", ".join(SoCBusHandler.supported_standard)))
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parser.add_argument("--bus-data-width", default=32, type=auto_int,
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help="Bus data width (default=32)")
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parser.add_argument("--bus-address-width", default=32, type=auto_int,
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help="Bus address width (default=32)")
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parser.add_argument("--bus-timeout", default=1e6, type=float,
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help="Bus timeout in cycles (default=1e6)")
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parser.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}, (default=wishbone).".format(", ".join(SoCBusHandler.supported_standard)))
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parser.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width (default=32).")
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parser.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width (default=32).")
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parser.add_argument("--bus-timeout", default=1e6, type=float, help="Bus timeout in cycles (default=1e6).")
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# CPU parameters
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parser.add_argument("--cpu-type", default=None,
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help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
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parser.add_argument("--cpu-variant", default=None,
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help="select CPU variant, (default=standard)")
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parser.add_argument("--cpu-reset-address", default=None, type=auto_int,
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help="CPU reset address (default=None (Integrated ROM)")
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# ROM parameters
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parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int,
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help="size/enable the integrated (BIOS) ROM (default=32KB)")
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parser.add_argument("--integrated-rom-file", default=None, type=str,
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help="integrated (BIOS) ROM binary file")
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# SRAM parameters
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parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int,
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help="size/enable the integrated SRAM (default=8KB)")
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# MAIN_RAM parameters
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parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int,
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help="size/enable the integrated main RAM")
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# CSR parameters
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parser.add_argument("--csr-data-width", default=None, type=auto_int,
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help="CSR bus data-width (8 or 32, default=32)")
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parser.add_argument("--csr-address-width", default=14, type=auto_int,
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help="CSR bus address-width")
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parser.add_argument("--csr-paging", default=0x800, type=auto_int,
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help="CSR bus paging")
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parser.add_argument("--csr-ordering", default="big",
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help="CSR registers ordering (default=big)")
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# Identifier parameters
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parser.add_argument("--ident", default=None, type=str,
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help="SoC identifier (default=\"\"")
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parser.add_argument("--ident-version", default=None, type=bool,
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help="add date/time to SoC identifier (default=False)")
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# UART parameters
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parser.add_argument("--no-uart", action="store_true",
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help="Disable UART (default=False)")
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parser.add_argument("--uart-name", default="serial", type=str,
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help="UART type/name (default=serial)")
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parser.add_argument("--uart-baudrate", default=None, type=auto_int,
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help="UART baudrate (default=115200)")
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parser.add_argument("--uart-fifo-depth", default=16, type=auto_int,
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help="UART FIFO depth (default=16)")
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# Timer parameters
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parser.add_argument("--no-timer", action="store_true",
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help="Disable Timer (default=False)")
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parser.add_argument("--timer-uptime", action="store_true",
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help="Add an uptime register to the timer (default=False)")
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parser.add_argument("--cpu-type", default=None, help="Select CPU: {}, (default=vexriscv).".format(", ".join(iter(cpu.CPUS.keys()))))
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parser.add_argument("--cpu-variant", default=None, help="CPU variant (default=standard).")
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parser.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (default=None : Boot from Integrated ROM).")
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# Controller parameters
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parser.add_argument("--no-ctrl", action="store_true",
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help="Disable Controller (default=False)")
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parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=False).")
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# ROM parameters
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parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=32KB).")
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parser.add_argument("--integrated-rom-file", default=None, type=str, help="Integrated (BIOS) ROM binary file.")
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# SRAM parameters
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parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM (default=8KB).")
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# MAIN_RAM parameters
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parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM")
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# CSR parameters
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parser.add_argument("--csr-data-width", default=None, type=auto_int, help="CSR bus data-width (8 or 32, default=32).")
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parser.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width.")
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parser.add_argument("--csr-paging", default=0x800, type=auto_int, help="CSR bus paging.")
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parser.add_argument("--csr-ordering", default="big", help="CSR registers ordering (default=big).")
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# Identifier parameters
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parser.add_argument("--ident", default=None, type=str, help="SoC identifier (default=\"\").")
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parser.add_argument("--ident-version", default=None, type=bool, help="Add date/time to SoC identifier (default=False)")
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# UART parameters
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parser.add_argument("--no-uart", action="store_true", help="Disable UART (default=False).")
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parser.add_argument("--uart-name", default="serial", type=str, help="UART type/name (default=serial).")
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parser.add_argument("--uart-baudrate", default=None, type=auto_int, help="UART baudrate (default=115200).")
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parser.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth (default=16).")
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# Timer parameters
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parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).")
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parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).")
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def soc_core_argdict(args):
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r = dict()
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