build/generic_platform: Minor cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
9d08c65e8a
commit
da1277021a
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@ -18,11 +18,14 @@ from litex.gen.fhdl import verilog
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from litex.build.io import CRG
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from litex.build import tools
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# --------------------------------------------------------------------------------------------------
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class ConstraintError(Exception):
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pass
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# IOS ----------------------------------------------------------------------------------------------
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class Pins:
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def __init__(self, *identifiers):
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self.identifiers = []
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@ -33,8 +36,7 @@ class Pins:
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self.identifiers += i.split()
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def __repr__(self):
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return "{}('{}')".format(self.__class__.__name__,
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" ".join(self.identifiers))
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return "{}('{}')".format(self.__class__.__name__, " ".join(self.identifiers))
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class IOStandard:
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@ -69,15 +71,15 @@ class Inverted:
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class Subsignal:
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def __init__(self, name, *constraints):
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self.name = name
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self.name = name
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self.constraints = list(constraints)
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def __repr__(self):
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return "{}('{}', {})".format(
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self.__class__.__name__,
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return "{}('{}', {})".format(self.__class__.__name__,
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self.name,
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", ".join([repr(constr) for constr in self.constraints]))
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# Platform -----------------------------------------------------------------------------------------
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class PlatformInfo:
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def __init__(self, info):
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@ -111,7 +113,7 @@ def _resource_type(resource):
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i = []
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assert(isinstance(t, list))
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n_bits = None
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n_bits = None
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inverted = False
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for c in element.constraints:
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if isinstance(c, Pins):
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@ -125,12 +127,13 @@ def _resource_type(resource):
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return t, i
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# Connector Manager --------------------------------------------------------------------------------
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class ConnectorManager:
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def __init__(self, connectors):
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self.connector_table = dict()
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for connector in connectors:
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cit = iter(connector)
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cit = iter(connector)
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conn_name = next(cit)
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if isinstance(connector[1], str):
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pin_list = []
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@ -164,7 +167,7 @@ class ConnectorManager:
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def _separate_pins(constraints):
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pins = None
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pins = None
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others = []
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for c in constraints:
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if isinstance(c, Pins):
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@ -175,11 +178,12 @@ def _separate_pins(constraints):
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return pins, others
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# Constraint Manager -------------------------------------------------------------------------------
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class ConstraintManager:
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def __init__(self, io, connectors):
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self.available = list(io)
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self.matched = []
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self.available = list(io)
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self.matched = []
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self.platform_commands = []
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self.connector_manager = ConnectorManager(connectors)
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@ -258,9 +262,9 @@ class ConstraintManager:
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def get_sig_constraints(self):
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r = []
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for resource, obj in self.matched:
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name = resource[0]
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number = resource[1]
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has_subsignals = False
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name = resource[0]
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number = resource[1]
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has_subsignals = False
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top_constraints = []
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for element in resource[2:]:
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if isinstance(element, Subsignal):
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@ -287,10 +291,11 @@ class ConstraintManager:
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def get_platform_commands(self):
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return self.platform_commands
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# Generic Platform ---------------------------------------------------------------------------------
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class GenericPlatform:
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def __init__(self, device, io, connectors=[], name=None):
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self.device = device
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self.device = device
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self.constraint_manager = ConstraintManager(io, connectors)
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if name is None:
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# Get name from Platform file.
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@ -298,12 +303,12 @@ class GenericPlatform:
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if name == "__main__":
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# If no Platform file, use script filename,
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name = os.path.splitext(os.path.basename(sys.argv[0]))[0]
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self.name = name
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self.sources = []
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self.name = name
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self.sources = []
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self.verilog_include_paths = []
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self.output_dir = None
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self.finalized = False
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self.use_default_clk = False
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self.output_dir = None
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self.finalized = False
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self.use_default_clk = False
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def request(self, *args, **kwargs):
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return self.constraint_manager.request(*args, **kwargs)
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@ -335,7 +340,7 @@ class GenericPlatform:
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def finalize(self, fragment, *args, **kwargs):
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if self.finalized:
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raise ConstraintError("Already finalized")
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# if none exists, create a default clock domain and drive it
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# If none exists, create a default clock domain and drive it.
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if not fragment.clock_domains:
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if not hasattr(self, "default_clk_name"):
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raise NotImplementedError(
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@ -348,8 +353,7 @@ class GenericPlatform:
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self.finalized = True
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def do_finalize(self, fragment, *args, **kwargs):
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"""overload this and e.g. add_platform_command()'s after the modules
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had their say"""
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# Overload this and e.g. add_platform_command()'s after the modules had their say.
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if self.use_default_clk and hasattr(self, "default_clk_period"):
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try:
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self.add_period_constraint(
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@ -393,11 +397,11 @@ class GenericPlatform:
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self.verilog_include_paths.append(os.path.abspath(path))
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def resolve_signals(self, vns):
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# resolve signal names in constraints
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# Resolve signal names in constraints.
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sc = self.constraint_manager.get_sig_constraints()
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named_sc = [(vns.get_name(sig), pins, others, resource)
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for sig, pins, others, resource in sc]
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# resolve signal names in platform commands
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# Resolve signal names in platform commands.
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pc = self.constraint_manager.get_platform_commands()
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named_pc = []
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for template, args in pc:
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