build/generic_platform: Minor cosmetic cleanups.

litex/build/generic_platform.py

@@ -18,11 +18,14 @@ from litex.gen.fhdl import verilog
 from litex.build.io import CRG
 from litex.build import tools
 
+# --------------------------------------------------------------------------------------------------
 
 class ConstraintError(Exception):
     pass
 
 
+# IOS ----------------------------------------------------------------------------------------------
+
 class Pins:
     def __init__(self, *identifiers):
         self.identifiers = []
@@ -33,8 +36,7 @@ class Pins:
                 self.identifiers += i.split()
 
     def __repr__(self):
-        return "{}('{}')".format(self.__class__.__name__,
-                                 " ".join(self.identifiers))
+        return "{}('{}')".format(self.__class__.__name__, " ".join(self.identifiers))
 
 
 class IOStandard:
@@ -73,11 +75,11 @@ class Subsignal:
         self.constraints = list(constraints)
 
     def __repr__(self):
-        return "{}('{}', {})".format(
-            self.__class__.__name__,
+        return "{}('{}', {})".format(self.__class__.__name__,
             self.name,
             ", ".join([repr(constr) for constr in self.constraints]))
 
+# Platform -----------------------------------------------------------------------------------------
 
 class PlatformInfo:
     def __init__(self, info):
@@ -125,6 +127,7 @@ def _resource_type(resource):
 
     return t, i
 
+# Connector Manager --------------------------------------------------------------------------------
 
 class ConnectorManager:
     def __init__(self, connectors):
@@ -175,6 +178,7 @@ def _separate_pins(constraints):
 
     return pins, others
 
+# Constraint Manager -------------------------------------------------------------------------------
 
 class ConstraintManager:
     def __init__(self, io, connectors):
@@ -287,6 +291,7 @@ class ConstraintManager:
     def get_platform_commands(self):
         return self.platform_commands
 
+# Generic Platform ---------------------------------------------------------------------------------
 
 class GenericPlatform:
     def __init__(self, device, io, connectors=[], name=None):
@@ -335,7 +340,7 @@ class GenericPlatform:
     def finalize(self, fragment, *args, **kwargs):
         if self.finalized:
             raise ConstraintError("Already finalized")
-        # if none exists, create a default clock domain and drive it
+        # If none exists, create a default clock domain and drive it.
         if not fragment.clock_domains:
             if not hasattr(self, "default_clk_name"):
                 raise NotImplementedError(
@@ -348,8 +353,7 @@ class GenericPlatform:
         self.finalized = True
 
     def do_finalize(self, fragment, *args, **kwargs):
-        """overload this and e.g. add_platform_command()'s after the modules
-        had their say"""
+        # Overload this and e.g. add_platform_command()'s after the modules had their say.
         if self.use_default_clk and hasattr(self, "default_clk_period"):
             try:
                 self.add_period_constraint(
@@ -393,11 +397,11 @@ class GenericPlatform:
         self.verilog_include_paths.append(os.path.abspath(path))
 
     def resolve_signals(self, vns):
-        # resolve signal names in constraints
+        # Resolve signal names in constraints.
         sc = self.constraint_manager.get_sig_constraints()
         named_sc = [(vns.get_name(sig), pins, others, resource)
                     for sig, pins, others, resource in sc]
-        # resolve signal names in platform commands
+        # Resolve signal names in platform commands.
         pc = self.constraint_manager.get_platform_commands()
         named_pc = []
         for template, args in pc: