bus: 14-bit CSR addresses

This commit is contained in:
Sebastien Bourdeauducq 2011-12-11 20:16:50 +01:00
parent 7582b76406
commit dad9120653
2 changed files with 2 additions and 2 deletions

View File

@ -2,7 +2,7 @@ from migen.fhdl import structure as f
from .simple import Simple from .simple import Simple
_desc = [ _desc = [
(True, "a", 16), (True, "a", 14),
(True, "we", 1), (True, "we", 1),
(True, "d", 32), (True, "d", 32),
(False, "d", 32) (False, "d", 32)

View File

@ -14,7 +14,7 @@ class Inst():
sync = [ sync = [
f.Assign(self.csr.we_o, self.wishbone.we_i), f.Assign(self.csr.we_o, self.wishbone.we_i),
f.Assign(self.csr.d_o, self.wishbone.dat_i), f.Assign(self.csr.d_o, self.wishbone.dat_i),
f.Assign(self.csr.a_o, self.wishbone.adr_i[:16]), f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]),
f.Assign(self.wishbone.ack_o, 0), f.Assign(self.wishbone.ack_o, 0),
f.Assign(self.wishbone.dat_o, self.csr.d_i) f.Assign(self.wishbone.dat_o, self.csr.d_i)
] ]