tools/litex_json2renode: Update PLIC interrupt configuration
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@ -433,12 +433,12 @@ clint: IRQControllers.CoreLevelInterruptor @ {}
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def generate_plic(plic):
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def generate_plic(plic):
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# TODO: this is configuration for VexRiscv - add support for other CPU types
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# TODO: this is configuration for linux-on-litex-vexriscv - add support for other CPU types
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result = """
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result = """
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plic: IRQControllers.PlatformLevelInterruptController @ {}
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plic: IRQControllers.PlatformLevelInterruptController @ {}
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[0-3] -> cpu@[8-11]
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[0, 1] -> cpu@[11, 9]
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numberOfSources: 31
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numberOfSources: 31
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numberOfTargets: 2
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numberOfContexts: 2
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prioritiesEnabled: false
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prioritiesEnabled: false
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""".format(generate_sysbus_registration(plic,
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""".format(generate_sysbus_registration(plic,
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skip_braces=True,
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skip_braces=True,
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