mirror of
https://github.com/enjoy-digital/litex.git
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fix uart2Csr and update miio example
This commit is contained in:
Florent Kermarrec
parent
24211574ec
commit
db1ceccca1
11 changed files with 246 additions and 213 deletions
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@ -10,6 +10,10 @@ def main():
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# set pin constraints
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plat.request("led", 0, obj=soc.led)
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#plat.request("led", 4, obj=soc.uart_rx_event.o)
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#plat.request("led", 5, obj=soc.uart_tx_event.o)
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#plat.request("led", 7, obj=soc.debug_event.o)
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plat.request("serial", 0, obj=soc.uart2csr)
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# set extra constraints
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@ -1,79 +0,0 @@
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 4096
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# Csr Addr
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MIIO_ADDR = 0x0000
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MILA_ADDR = 0x0200
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csr = Uart2Spi(1, 115200, debug=False)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr)
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# miLa0
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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#==============================================================================
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dat_vcd = []
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recorder0.size(1024)
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def capture(size):
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global trigger0
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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miLa0.trig.sum.write(sum_tt)
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miLa0.rec.reset()
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miLa0.rec.offset(0)
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miLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not miLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += miLa0.rec.read(size)
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print("[Done]")
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print("Capturing Ramp..")
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print("----------------------")
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term0.write(0x0000,0xFFFF)
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csr.write(0x0000, 0)
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capture(1024)
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print("Capturing Square..")
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print("----------------------")
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term0.write(0x0000,0xFFFF)
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csr.write(0x0000, 1)
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capture(1024)
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print("Capturing Sinus..")
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print("----------------------")
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term0.write(0x0080,0xFFFF)
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csr.write(0x0000, 2)
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capture(1024)
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myvcd = Vcd()
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myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
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myvcd.write("test_MiLa_0.vcd")
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@ -1,62 +0,0 @@
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 32
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dat_width = 32
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# Record Size
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record_size = 4096
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# Csr Addr
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MIIO0_ADDR = 0x0000
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MILA1_ADDR = 0x0600
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csr = Uart2Spi(1, 115200, debug=False)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr)
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# miLa1
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term1 = trigger.Term(trig_width)
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trigger1 = trigger.Trigger(trig_width, [term1])
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recorder1 = recorder.Recorder(dat_width, record_size)
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miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr)
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#==============================================================================
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# T E S T M I G L A
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#==============================================================================
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dat_vcd = []
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recorder1.size(1024)
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term1.write(0x0100005A,0x0100005A)
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sum_tt = gen_truth_table("term1")
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miLa1.trig.sum.write(sum_tt)
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miLa1.rec.reset()
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miLa1.rec.offset(256)
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miLa1.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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csr.write(0x0000,0x5A)
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while(not miLa1.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += miLa1.rec.read(1024)
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print("[Done]")
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myvcd = Vcd()
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myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
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myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
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myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
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myvcd.write("test_MiLa_1.vcd")
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@ -1,44 +1,37 @@
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from miscope import trigger, recorder, miIo
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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from miscope import miio
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from miscope.bridges.uart2csr.tools.uart2Csr import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 1024
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csr = Uart2Spi(1,115200)
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csr = Uart2Csr(3,115200)
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# Csr Addr
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MIIO_ADDR = 0x0000
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# Miscope Configuration
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# miIo
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miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr)
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miio = miio.MiIo(MIIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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miIo0.write(0xA5)
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miio.write(0xA5)
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time.sleep(0.1)
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miIo0.write(0x5A)
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miio.write(0x5A)
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time.sleep(0.1)
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def led_anim1():
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#Led <<
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for j in range(4):
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#Led <<
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ledData = 1
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for i in range(8):
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miIo0.write(ledData)
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miio.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData<<1)
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#Led >>
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ledData = 128
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for i in range(8):
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miIo0.write(ledData)
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miio.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData>>1)
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@ -53,6 +46,4 @@ led_anim1()
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time.sleep(1)
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print("- Read Switch: ",end=' ')
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print(miIo0.read())
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print("%02X" %miio.read())
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111
examples/de0_nano/misc.py
Normal file
111
examples/de0_nano/misc.py
Normal file
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@ -0,0 +1,111 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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class RisingEdge(Module):
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def __init__(self, i=None, o=None, domain="sys"):
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self.i = ifthenelse(i, i, Signal())
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self.o = ifthenelse(o, o, Signal())
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####
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i_d = Signal()
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sync =[i_d.eq(self.i)]
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self.comb +=[self.o.eq(self.i & ~i_d)]
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self._fragment += Fragment(sync={domain : sync})
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class FallingEdge(Module):
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def __init__(self, i=None, o=None, domain="sys"):
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self.i = ifthenelse(i, i, Signal())
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self.o = ifthenelse(o, o, Signal())
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####
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i_d = Signal()
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sync =[i_d.eq(self.i)]
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self.comb +=[self.o.eq(~self.i & i_d)]
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self._fragment += Fragment(sync={domain : sync})
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class FreqGen(Module):
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def __init__(self, clk_freq, freq, o=None):
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cnt_max = int(clk_freq/freq/2)
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width = bits_for(cnt_max)
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self.o = ifthenelse(o, o, Signal())
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####
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cnt = Signal(width)
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self.sync += [
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If(cnt >= cnt_max,
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cnt.eq(0),
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self.o.eq(~self.o)
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).Else(
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cnt.eq(cnt+1)
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)
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]
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RISING_EDGE = 1
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FALLING_EDGE = 0
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class EventGen(Module):
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def __init__(self, i=None, level=1, clk_freq=0, length=1, o=None):
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cnt_max = int(length*clk_freq)
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width = bits_for(cnt_max)
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self.i = ifthenelse(i, i, Signal())
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self.o = ifthenelse(o, o, Signal())
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###
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cnt = Signal(width)
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i_edge = Signal()
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if level == RISING_EDGE:
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self.submodules += RisingEdge(self.i, i_edge)
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elif level == FALLING_EDGE:
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self.submodules += FallingEdge(self.i, i_edge)
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self.sync += [
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If(i_edge == 1,
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cnt.eq(0),
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self.o.eq(1)
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).Elif(cnt >= cnt_max,
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self.o.eq(0)
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).Else(
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cnt.eq(cnt+1)
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),
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]
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class PwmGen(Module):
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def __init__(self, width, o=None):
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self.ratio = Signal(width)
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self.o = ifthenelse(o, o, Signal())
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###
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cnt = Signal(width)
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self.sync += [
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If(cnt == 0,
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self.o.eq(1)
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).Elif(cnt >= self.ratio,
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self.o.eq(0)
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),
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cnt.eq(cnt+1)
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]
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class Cascade(Module):
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def __init__(self, i=None, elements=None, o=None):
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self.i = ifthenelse(i, i, Signal())
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self.o = ifthenelse(o, o, Signal())
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self.comb +=[elements[0].i.eq(self.i)]
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self.comb +=[elements[i+1].i.eq(elements[i].o) for i in range(len(elements)-1)]
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self.comb +=[self.o.eq(elements[len(elements)-1].o)]
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class PwrOnRst(Module):
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def __init__(self, width, rst=None, simulation=False):
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self.rst = ifthenelse(rst, rst, Signal())
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###
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cnt = Signal(width)
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sync_no_reset = [If(self.rst, cnt.eq(cnt+1))]
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if not simulation:
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self.comb +=[
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If(cnt >= (2**width-1),
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self.rst.eq(0)
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).Else(
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self.rst.eq(1)
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)
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]
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else:
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self.comb += self.rst.eq(0)
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self._fragment += Fragment(sync={"sys_no_reset" : sync_no_reset})
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@ -7,8 +7,8 @@
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#
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# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# miscope example on De0 Nano
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# ---------------------------
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# miscope miio example on De0 Nano
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# --------------------------------
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################################################################################
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#==============================================================================
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@ -38,8 +38,8 @@ MIIO0_ADDR = 0x0000
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#==============================================================================
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class SoC(Module):
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def __init__(self):
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# migIo0
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self.submodules.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# MiIo
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self.submodules.miio = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# Uart2Csr
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self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
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@ -47,11 +47,15 @@ class SoC(Module):
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# Csr Interconnect
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self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr,
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[
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self.miIo0.bank.bus
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self.miio.bank.bus
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])
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self.led = Signal()
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###
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# Led
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self.comb += self.led.eq(self.miIo0.o[0])
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self.led = Signal(8)
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###
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# Output
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self.comb += self.led.eq(self.miio.o)
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# Input
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self.comb += self.miio.i.eq(0x5A)
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@ -38,14 +38,14 @@ class Uart2Csr(Module):
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addr = Signal(32)
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data = Signal(8)
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# FSM
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self.submodules.fsm = FSM("IDLE",
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"GET_BL", "GET_ADDR",
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"GET_DATA", "WRITE_CSR",
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"READ_CSR", "SEND_DATA")
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"READ_CSR0", "READ_CSR1", "SEND_DATA")
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fsm = self.fsm
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#
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# Global
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#
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@ -53,13 +53,13 @@ class Uart2Csr(Module):
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If(fsm.ongoing(fsm.IDLE), cnt.eq(0)
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).Elif(uart.rx_ev, cnt.eq(cnt + 1)),
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sr.eq(Cat(uart.rx_dat, sr[0:24]))
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If(uart.rx_ev, sr.eq(Cat(uart.rx_dat, sr[0:24])))
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]
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# State done
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# State done signals
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get_bl_done = Signal()
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get_addr_done = Signal()
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get_addr_done_d = Signal()
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get_data_done = Signal()
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send_data_done = Signal()
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@ -72,12 +72,7 @@ class Uart2Csr(Module):
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)
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)
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self.sync +=[
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If(fsm.ongoing(fsm.IDLE) & uart.rx_ev,
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cmd.eq(uart.rx_dat)
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)
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]
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self.sync += If(fsm.ongoing(fsm.IDLE) & uart.rx_ev, cmd.eq(uart.rx_dat))
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#
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# Get burst length
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@ -90,11 +85,7 @@ class Uart2Csr(Module):
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self.comb += get_bl_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_BL))
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self.sync +=[
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If(get_bl_done,
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burst_cnt.eq(uart.rx_dat)
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)
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]
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self.sync += If(get_bl_done, burst_cnt.eq(uart.rx_dat))
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#
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# Get address
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@ -103,17 +94,18 @@ class Uart2Csr(Module):
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If(get_addr_done & (cmd == WRITE_CMD),
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fsm.next_state(fsm.GET_DATA)
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).Elif(get_addr_done & (cmd == READ_CMD),
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fsm.next_state(fsm.READ_CSR)
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fsm.next_state(fsm.READ_CSR0)
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)
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)
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self.comb += get_addr_done.eq(uart.rx_ev & (cnt == 4) & fsm.ongoing(fsm.GET_ADDR))
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self.sync += get_addr_done_d.eq(get_addr_done)
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self.sync += [
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If(get_addr_done,
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If(get_addr_done_d,
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addr.eq(sr)
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).Elif(get_data_done | send_data_done,
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addr.eq(addr + 4)
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).Elif(fsm.leaving(fsm.WRITE_CSR) | send_data_done,
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addr.eq(addr + 1)
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)
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]
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@ -122,12 +114,11 @@ class Uart2Csr(Module):
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#
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fsm.act(fsm.GET_DATA,
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If(get_data_done,
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fsm.next_state(fsm.IDLE)
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fsm.next_state(fsm.WRITE_CSR)
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)
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)
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self.comb += get_data_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_DATA))
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self.sync += [
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If(get_data_done,
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burst_cnt.eq(burst_cnt-1),
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@ -139,40 +130,53 @@ class Uart2Csr(Module):
|
|||
# Write Csr
|
||||
#
|
||||
fsm.act(fsm.WRITE_CSR,
|
||||
If((not burst_cnt),
|
||||
If((burst_cnt==0),
|
||||
fsm.next_state(fsm.IDLE)
|
||||
).Else(fsm.next_state(fsm.GET_DATA))
|
||||
)
|
||||
|
||||
|
||||
#
|
||||
# Read Csr
|
||||
# Read Csr0
|
||||
#
|
||||
fsm.act(fsm.READ_CSR,
|
||||
fsm.act(fsm.READ_CSR0,
|
||||
fsm.next_state(fsm.READ_CSR1)
|
||||
)
|
||||
|
||||
self.sync += If(fsm.entering(fsm.READ_CSR0), burst_cnt.eq(burst_cnt-1))
|
||||
|
||||
#
|
||||
# Read Csr1
|
||||
#
|
||||
fsm.act(fsm.READ_CSR1,
|
||||
fsm.next_state(fsm.SEND_DATA)
|
||||
)
|
||||
|
||||
|
||||
#
|
||||
# Send Data
|
||||
#
|
||||
fsm.act(fsm.SEND_DATA,
|
||||
If(send_data_done & (not burst_cnt),
|
||||
If(send_data_done & (burst_cnt==0),
|
||||
fsm.next_state(fsm.IDLE)
|
||||
).Elif(send_data_done,
|
||||
fsm.next_state(fsm.READ_CSR)
|
||||
fsm.next_state(fsm.READ_CSR0)
|
||||
)
|
||||
)
|
||||
|
||||
self.comb += [
|
||||
self.comb += send_data_done.eq(fsm.ongoing(fsm.SEND_DATA) & uart.tx_ev)
|
||||
|
||||
self.sync += [
|
||||
uart.tx_dat.eq(self.csr.dat_r),
|
||||
uart.tx_we.eq(fsm.entering(fsm.SEND_DATA)),
|
||||
send_data_done.eq(~uart.tx_we | uart.tx_ev)
|
||||
]
|
||||
|
||||
|
||||
#
|
||||
# Csr access
|
||||
#
|
||||
self.comb += self.csr.adr.eq(addr)
|
||||
self.sync +=[
|
||||
self.csr.adr.eq(addr),
|
||||
self.csr.dat_w.eq(data),
|
||||
If(fsm.ongoing(fsm.WRITE_CSR),
|
||||
self.csr.we.eq(1)
|
||||
|
|
@ -180,5 +184,3 @@ class Uart2Csr(Module):
|
|||
self.csr.we.eq(0)
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
|
|
|
|||
0
miscope/bridges/uart2csr/tools/__init__.py
Normal file
0
miscope/bridges/uart2csr/tools/__init__.py
Normal file
59
miscope/bridges/uart2csr/tools/uart2Csr.py
Normal file
59
miscope/bridges/uart2csr/tools/uart2Csr.py
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
import string
|
||||
import time
|
||||
import serial
|
||||
from struct import *
|
||||
import time
|
||||
|
||||
WRITE_CMD = 0x01
|
||||
READ_CMD = 0x02
|
||||
CLOSE_CMD = 0x03
|
||||
|
||||
def write_b(uart, data):
|
||||
uart.write(pack('B',data))
|
||||
|
||||
class Uart2Csr:
|
||||
def __init__(self, port, baudrate, debug=False):
|
||||
self.port = port
|
||||
self.baudrate = baudrate
|
||||
self.debug = debug
|
||||
self.uart = serial.Serial(port, baudrate, timeout=0.25)
|
||||
|
||||
def read(self, addr, burst_length=1):
|
||||
write_b(self.uart, READ_CMD)
|
||||
write_b(self.uart, burst_length)
|
||||
write_b(self.uart, (addr & 0xff000000) >> 24)
|
||||
write_b(self.uart, (addr & 0x00ff0000) >> 16)
|
||||
write_b(self.uart, (addr & 0x0000ff00) >> 8)
|
||||
write_b(self.uart, (addr & 0x000000ff))
|
||||
values = []
|
||||
for i in range(burst_length):
|
||||
read = self.uart.read(1)
|
||||
val = int(read[0])
|
||||
if self.debug:
|
||||
print("RD %02X @ %08X" %(val, addr + 4*i))
|
||||
values.append(val)
|
||||
if burst_length == 1:
|
||||
return values[0]
|
||||
else:
|
||||
return values
|
||||
|
||||
def write(self, addr, data):
|
||||
if isinstance(data, list):
|
||||
burst_length = len(data)
|
||||
else:
|
||||
burst_length = 1
|
||||
write_b(self.uart, WRITE_CMD)
|
||||
write_b(self.uart, burst_length)
|
||||
self.uart.write([(addr & 0xff000000) >> 24,
|
||||
(addr & 0x00ff0000) >> 16,
|
||||
(addr & 0x0000ff00) >> 8,
|
||||
(addr & 0x000000ff)])
|
||||
if isinstance(data, list):
|
||||
for i in range(len(data)):
|
||||
write_b(self.uart, data[i])
|
||||
if self.debug:
|
||||
print("WR %02X @ %08X" %(elt, addr + 4*i))
|
||||
else:
|
||||
write_b(self.uart, data)
|
||||
if self.debug:
|
||||
print("WR %02X @ %08X" %(data, addr))
|
||||
|
|
@ -19,6 +19,7 @@ class UART(Module):
|
|||
self.tx = Signal(reset=1)
|
||||
self.rx = Signal()
|
||||
|
||||
|
||||
###
|
||||
|
||||
enable16 = Signal()
|
||||
|
|
@ -34,8 +35,10 @@ class UART(Module):
|
|||
tx_reg = Signal(8)
|
||||
tx_bitcount = Signal(4)
|
||||
tx_count16 = Signal(4)
|
||||
tx_busy = self.tx_ev
|
||||
tx_done = self.tx_ev
|
||||
tx_busy = Signal()
|
||||
self.sync += [
|
||||
tx_done.eq(0),
|
||||
If(self.tx_we,
|
||||
tx_reg.eq(self.tx_dat),
|
||||
tx_bitcount.eq(0),
|
||||
|
|
@ -50,7 +53,8 @@ class UART(Module):
|
|||
self.tx.eq(1)
|
||||
).Elif(tx_bitcount == 9,
|
||||
self.tx.eq(1),
|
||||
tx_busy.eq(0)
|
||||
tx_busy.eq(0),
|
||||
tx_done.eq(1)
|
||||
).Else(
|
||||
self.tx.eq(tx_reg[0]),
|
||||
tx_reg.eq(Cat(tx_reg[1:], 0))
|
||||
|
|
|
|||
|
|
@ -38,8 +38,7 @@ class MiIo:
|
|||
#Driver
|
||||
#
|
||||
def write(self, data):
|
||||
self.interface.write(self.address, data, self.width)
|
||||
self.interface.write(self.address, data)
|
||||
|
||||
def read(self):
|
||||
r = self.interface.read(self.address + self.words, self.width)
|
||||
return r
|
||||
return self.interface.read(self.address + self.words)
|
||||
Loading…
Reference in a new issue