61 lines
1.9 KiB
Python
61 lines
1.9 KiB
Python
################################################################################
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# _____ _ ____ _ _ _ _
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# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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# | __| | | | . | | | | | | | . | | _| .'| |
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# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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# |___| |___| |___|
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#
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# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# miscope miio example on De0 Nano
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# --------------------------------
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################################################################################
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.bus import csr
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from miscope import miio
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from miscope.bridges import uart2csr
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from timings import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Timings Param
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clk_freq = 50*MHz
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# Csr Addr
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MIIO0_ADDR = 0x0000
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#==============================================================================
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# M I S C O P E E X A M P L E
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#==============================================================================
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class SoC(Module):
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def __init__(self):
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# MiIo
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self.submodules.miio = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# Uart2Csr
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self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
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# Csr Interconnect
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self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr,
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[
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self.miio.bank.bus
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])
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# Led
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self.led = Signal(8)
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###
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# Output
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self.comb += self.led.eq(self.miio.o)
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# Input
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self.comb += self.miio.i.eq(0x5A) |