litex/examples/de0_nano/top.py

61 lines
1.9 KiB
Python
Raw Normal View History

2012-09-09 16:32:09 -04:00
################################################################################
# _____ _ ____ _ _ _ _
# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
# | __| | | | . | | | | | | | . | | _| .'| |
# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
# |___| |___| |___|
#
# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
2012-09-09 16:32:09 -04:00
#
2013-03-18 18:57:51 -04:00
# miscope miio example on De0 Nano
# --------------------------------
2012-09-09 16:32:09 -04:00
################################################################################
2012-09-09 15:18:09 -04:00
#==============================================================================
# I M P O R T
#==============================================================================
from migen.fhdl.structure import *
from migen.fhdl.module import *
2012-09-09 16:32:09 -04:00
from migen.bus import csr
from miscope import miio
from miscope.bridges import uart2csr
2012-09-09 15:18:09 -04:00
from timings import *
#==============================================================================
# P A R A M E T E R S
#==============================================================================
2013-03-18 18:57:51 -04:00
# Timings Param
2012-09-09 15:18:09 -04:00
clk_freq = 50*MHz
2012-09-09 16:32:09 -04:00
# Csr Addr
2013-02-26 17:00:28 -05:00
MIIO0_ADDR = 0x0000
2012-09-09 16:32:09 -04:00
2012-09-09 15:18:09 -04:00
#==============================================================================
2013-03-18 18:57:51 -04:00
# M I S C O P E E X A M P L E
2012-09-09 15:18:09 -04:00
#==============================================================================
class SoC(Module):
2013-02-28 16:40:35 -05:00
def __init__(self):
2013-03-18 18:57:51 -04:00
# MiIo
self.submodules.miio = miio.MiIo(MIIO0_ADDR, 8, "IO")
2013-02-28 16:40:35 -05:00
# Uart2Csr
self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
2013-02-28 16:40:35 -05:00
# Csr Interconnect
self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr,
2013-02-28 16:40:35 -05:00
[
2013-03-18 18:57:51 -04:00
self.miio.bank.bus
2013-02-28 16:40:35 -05:00
])
2013-03-18 18:57:51 -04:00
2013-02-28 16:40:35 -05:00
# Led
2013-03-18 18:57:51 -04:00
self.led = Signal(8)
###
# Output
self.comb += self.led.eq(self.miio.o)
# Input
self.comb += self.miio.i.eq(0x5A)