integration/soc: warn about overrides only on differences

2022-01-15 17:13:48 +01:00 · 2022-01-15 17:13:48 +01:00 · db9d40a5a0
parent f8863bb986
commit db9d40a5a0
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -926,7 +926,7 @@ class SoC(Module):
        else:
            # Override User's mapping with CPU constrainted mapping (and warn User).
            for n, origin in self.cpu.mem_map.items():
-                if n in self.mem_map.keys():
+                if n in self.mem_map.keys() and self.mem_map[n] != self.cpu.mem_map[n]:
                    self.logger.info("CPU {} {} mapping from {} to {}.".format(
                        colorer("overriding", color="cyan"),
                        colorer(n),