Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/sim: switch from shadow_base to io_regions

This commit is contained in:
Florent Kermarrec 2019-10-09 10:38:22 +02:00
parent 10146abf0a
commit dc656d48c2
10 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/boards/targets/arty.py
View File

@ -73,7 +73,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -86,7 +86,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/genesys2.py
View File

@ -65,7 +65,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/kc705.py
View File

@ -67,7 +67,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/kcu105.py
View File

@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/netv2.py
View File

@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/nexys4ddr.py
View File

@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/nexys_video.py
View File

@ -70,7 +70,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/simple.py
View File

@ -31,7 +31,7 @@ class BaseSoC(SoCCore):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/boards/targets/versa_ecp5.py
View File

@ -104,7 +104,7 @@ class BaseSoC(SoCSDRAM):
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC):
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

4
litex/tools/litex_sim.py
View File

@ -88,7 +88,7 @@ class Platform(SimPlatform):
class SimSoC(SoCSDRAM):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0xb0000000,
}
mem_map.update(SoCSDRAM.mem_map)
@ -153,7 +153,7 @@ class SimSoC(SoCSDRAM):
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
self.add_csr("ethmac")
self.add_interrupt("ethmac")