Merge branch 'master' into generic_toolchain
This commit is contained in:
commit
dc6b81a13f
|
@ -10,11 +10,15 @@ jobs:
|
|||
- name: Checkout
|
||||
uses: actions/checkout@v2
|
||||
|
||||
- name: Setup CCache
|
||||
uses: hendrikmuhs/ccache-action@v1
|
||||
|
||||
# Install Tools
|
||||
- name: Install Tools
|
||||
run: |
|
||||
sudo apt-get install wget build-essential python3 ninja-build
|
||||
sudo apt-get install verilator libevent-dev libjson-c-dev
|
||||
sudo apt-get install libevent-dev libjson-c-dev flex bison
|
||||
sudo apt-get install libfl-dev libfl2 zlibc zlib1g-dev
|
||||
pip3 install setuptools
|
||||
pip3 install requests
|
||||
pip3 install pexpect
|
||||
|
@ -35,6 +39,17 @@ jobs:
|
|||
sudo mkdir /usr/local/openrisc
|
||||
sudo cp -r $PWD/../openrisc-*/* /usr/local/openrisc
|
||||
|
||||
# Build / Install Verilator
|
||||
- name: Build Verilator
|
||||
run: |
|
||||
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
|
||||
git clone https://github.com/verilator/verilator
|
||||
cd verilator
|
||||
autoconf
|
||||
./configure
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
|
||||
# Install Project
|
||||
- name: Install Project
|
||||
run: python3 setup.py develop --user
|
||||
|
|
|
@ -603,8 +603,8 @@ def get_csr_svd(soc, vendor="litex", name="soc", description=None):
|
|||
def get_memory_x(soc):
|
||||
r = get_linker_regions(soc.mem_regions)
|
||||
r += '\n'
|
||||
r += 'REGION_ALIAS("REGION_TEXT", spiflash);\n'
|
||||
r += 'REGION_ALIAS("REGION_RODATA", spiflash);\n'
|
||||
r += 'REGION_ALIAS("REGION_TEXT", rom);\n'
|
||||
r += 'REGION_ALIAS("REGION_RODATA", rom);\n'
|
||||
r += 'REGION_ALIAS("REGION_DATA", sram);\n'
|
||||
r += 'REGION_ALIAS("REGION_BSS", sram);\n'
|
||||
r += 'REGION_ALIAS("REGION_HEAP", sram);\n'
|
||||
|
|
|
@ -1638,6 +1638,7 @@ class LiteXSoC(SoC):
|
|||
ip_address = "192.168.1.50",
|
||||
udp_port = 1234,
|
||||
buffer_depth = 16,
|
||||
with_ip_broadcast = True,
|
||||
with_timing_constraints = True):
|
||||
# Imports
|
||||
from liteeth.core import LiteEthUDPIPCore
|
||||
|
@ -1654,6 +1655,7 @@ class LiteXSoC(SoC):
|
|||
ip_address = ip_address,
|
||||
clk_freq = self.clk_freq,
|
||||
dw = data_width,
|
||||
with_ip_broadcast = with_ip_broadcast,
|
||||
with_sys_datapath = with_sys_datapath,
|
||||
)
|
||||
if not with_sys_datapath:
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
* Initialize SDRAM (Init + Calibration)
|
||||
*
|
||||
*/
|
||||
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
|
||||
#if defined(CSR_SDRAM_BASE)
|
||||
define_command(sdram_init, sdram_init, "Initialize SDRAM (Init + Calibration)", LITEDRAM_CMDS);
|
||||
#endif
|
||||
|
||||
|
@ -317,7 +317,7 @@ define_command(sdram_force_bitslip, sdram_force_bitslip_handler, "Force write le
|
|||
* Write SDRAM Mode Register
|
||||
*
|
||||
*/
|
||||
#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
|
||||
#if defined(CSR_SDRAM_BASE)
|
||||
static void sdram_mr_write_handler(int nb_params, char **params)
|
||||
{
|
||||
char *c;
|
||||
|
|
|
@ -382,6 +382,7 @@ void sdcard_decode_csd(void) {
|
|||
|
||||
int sdcard_init(void) {
|
||||
uint16_t rca, timeout;
|
||||
uint32_t r[SD_CMD_RESPONSE_SIZE/4];
|
||||
|
||||
/* Set SD clk freq to Initialization frequency */
|
||||
sdcard_set_clk_freq(SDCARD_CLK_FREQ_INIT, 0);
|
||||
|
@ -411,8 +412,13 @@ int sdcard_init(void) {
|
|||
/* Set SDCard in Operational state */
|
||||
for (timeout=1000; timeout>0; timeout--) {
|
||||
sdcard_app_cmd(0);
|
||||
if (sdcard_app_send_op_cond(1) != SD_OK)
|
||||
break;
|
||||
if (sdcard_app_send_op_cond(1) == SD_OK) {
|
||||
csr_rd_buf_uint32(CSR_SDCORE_CMD_RESPONSE_ADDR,
|
||||
r, SD_CMD_RESPONSE_SIZE/4);
|
||||
|
||||
if (r[3] & 0x80000000) /* Busy bit, set when init is complete */
|
||||
break;
|
||||
}
|
||||
busy_wait(1);
|
||||
}
|
||||
if (timeout == 0)
|
||||
|
|
|
@ -41,10 +41,7 @@ class TestCPU(unittest.TestCase):
|
|||
"firev", # (riscv / softcore)
|
||||
"ibex", # (riscv / softcore)
|
||||
"marocchino", # (or1k / softcore)
|
||||
"mor1kx", # (or1k / softcore)
|
||||
"naxriscv", # (riscv / softcore)
|
||||
"picorv32", # (riscv / softcore)
|
||||
"rocket", # (riscv / softcore)
|
||||
"serv", # (riscv / softcore)
|
||||
"vexriscv", # (riscv / softcore)
|
||||
"vexriscv_smp", # (riscv / softcore)
|
||||
|
@ -61,7 +58,10 @@ class TestCPU(unittest.TestCase):
|
|||
"lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
|
||||
"microwatt", # (ppc64 / softcore) -> Requires PPC toolchain + VHDL->Verilog (GHDL + Yosys).
|
||||
"minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
|
||||
"mor1kx", # (or1k / softcore) -> Verilator compilation issue.
|
||||
"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).
|
||||
"picorv32", # (riscv / softcore) -> Verilator compilation issue.
|
||||
"rocket", # (riscv / softcore) -> Not enough RAM in CI.
|
||||
"zynq7000", # (arm / hardcore) -> Hardcore.
|
||||
"zynqmp", # (aarch64 / hardcore) -> Hardcore.
|
||||
]
|
||||
|
|
Loading…
Reference in New Issue