soc/interconnect/stream/ClockDomainCrossing: Add a Buffer when same Clk Domains when buffered=True.

litex/soc/interconnect/stream.py

@@ -254,6 +254,14 @@ class ClockDomainCrossing(LiteXModule, DUID):
 
         # Same Clk Domains.
         if cd_from == cd_to:
+            if buffered:
+                # Add Buffer.
+                self.buffer = ClockDomainsRenamer(cd_from)(Buffer(layout))
+                self.comb += [
+                    self.sink.connect(self.buffer.sink),
+                    self.buffer.source.connect(self.source),
+                ]
+            else:
                 # No adaptation.
                 self.comb += self.sink.connect(self.source)
         # Different Clk Domains.