soc/interconnect/stream/ClockDomainCrossing: Add a Buffer when same Clk Domains when buffered=True.

This commit is contained in:
Florent Kermarrec 2024-04-04 13:02:17 +02:00
parent a36fbc86ea
commit dc78c3f47b
1 changed files with 10 additions and 2 deletions

View File

@ -254,8 +254,16 @@ class ClockDomainCrossing(LiteXModule, DUID):
# Same Clk Domains. # Same Clk Domains.
if cd_from == cd_to: if cd_from == cd_to:
# No adaptation. if buffered:
self.comb += self.sink.connect(self.source) # Add Buffer.
self.buffer = ClockDomainsRenamer(cd_from)(Buffer(layout))
self.comb += [
self.sink.connect(self.buffer.sink),
self.buffer.source.connect(self.source),
]
else:
# No adaptation.
self.comb += self.sink.connect(self.source)
# Different Clk Domains. # Different Clk Domains.
else: else:
if with_common_rst: if with_common_rst: