Merge branch 'master' into vexiiriscv-macsg

litex/soc/cores/cpu/vexiiriscv/core.py

@@ -58,6 +58,7 @@ class VexiiRiscv(CPU):
     with_rva         = False
     with_dma         = False
     with_axi3        = False
+    with_opensbi     = False
     jtag_tap         = False
     jtag_instruction = False
     with_cpu_clk     = False
@@ -166,6 +167,7 @@ class VexiiRiscv(CPU):
         VexiiRiscv.vexii_args += " --relaxed-branch"
 
         if args.cpu_variant in ["linux", "debian"]:
+            VexiiRiscv.with_opensbi = True
             VexiiRiscv.vexii_args += " --with-rva --with-supervisor"
             VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64"
             VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64"
@@ -395,6 +397,7 @@ class VexiiRiscv(CPU):
         md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8'))
         md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8'))
         md5_hash.update(str(VexiiRiscv.vexii_macsg).encode('utf-8'))
+        md5_hash.update(str(VexiiRiscv.with_opensbi).encode('utf-8'))
 
         # md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8'))
 
@@ -473,12 +476,13 @@ class VexiiRiscv(CPU):
         # Set Human-name.
         self.human_name = f"{self.human_name} {self.xlen}-bit"
 
-        # Set UART/Timer0 CSRs to the ones used by OpenSBI.
-        soc.csr.add("uart",   n=2)
-        soc.csr.add("timer0", n=3)
+        if VexiiRiscv.with_opensbi:
+            # Set UART/Timer0 CSRs to the ones used by OpenSBI.
+            soc.csr.add("uart",   n=2)
+            soc.csr.add("timer0", n=3)
 
-        # Add OpenSBI region.
-        soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
+            # Add OpenSBI region.
+            soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
 
         # Define ISA.
         soc.add_config("CPU_COUNT", VexiiRiscv.cpu_count)

litex/soc/cores/led.py

@@ -137,7 +137,8 @@ class WS2812(LiteXModule):
             self.bus  = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         else:
             # Memory.
-            mem = Memory(32, nleds, init=init)
+            mem_depth = max(nleds, 2)
+            mem = Memory(32, mem_depth, init=init)
             port = mem.get_port()
             self.specials += mem, port
 

test/test_led.py

@@ -13,6 +13,7 @@ from litex.soc.cores.led import WS2812
 
 class TestWS2812(unittest.TestCase):
     test_clk_freqs = [75e6, 50e6, 25e6]
+    test_led_data = [0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000]
 
     def generator(self, dut, led_signal, led_data, sys_clk_freq, iterations):
         # Error Margin from WS2812 datasheet.
@@ -71,17 +72,21 @@ class TestWS2812(unittest.TestCase):
         return ( int(x) for x in bin(num)[2:].zfill(length) )
 
 
-    def run_test(self, revision, sys_clk_freq):
+    def run_test(self, revision, sys_clk_freq, led_data):
         led_signal = Signal()
-        led_data   = [0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000]
         iterations = 2
         dut = WS2812(led_signal, len(led_data), sys_clk_freq, revision=revision, init=led_data)
         run_simulation(dut, self.generator(dut, led_signal, led_data, sys_clk_freq, iterations), vcd_name="sim.vcd")
 
     def test_WS2812_old(self):
         for sys_clk_freq in self.test_clk_freqs:
-            self.run_test("old", sys_clk_freq)
+            self.run_test("old", sys_clk_freq, self.test_led_data)
 
     def test_WS2812_new(self):
         for sys_clk_freq in self.test_clk_freqs:
-            self.run_test("new", sys_clk_freq)
+            self.run_test("new", sys_clk_freq, self.test_led_data)
+
+    def test_WS2812_1led(self):
+        led_data = [0x100000]
+        for sys_clk_freq in self.test_clk_freqs:
+            self.run_test("old", sys_clk_freq, led_data)