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targets/arty: use new ISERDESE2 MEMORY mode.

This commit is contained in:
Florent Kermarrec 2020-03-20 18:58:31 +01:00
parent fca52d110d
commit dd7718b4fe
2 changed files with 12 additions and 5 deletions
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8
litex/boards/platforms/arty.py
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@ -109,8 +109,12 @@ _io = [
"V4 T5 U4 V5 V1 T3 U3 R3"), "V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL135"), IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")), Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")), Subsignal("dqs_p", Pins("N2 U2"),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")), IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("N1 V2"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")), Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")), Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL135")), Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),

9
litex/boards/targets/arty.py
View File

@ -27,6 +27,7 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
@ -38,6 +39,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
@ -62,9 +64,10 @@ class BaseSoC(SoCSDRAM):
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
interface_type = "MEMORY")
self.add_csr("ddrphy") self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4") sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,