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Split CSR documentation diagrams with more than 8 bits into multiple lanes. 

In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.

With this patch we split the register into multiple lanes of 8 bits
each.
This commit is contained in:
Piotr Esden-Tempski 2020-03-12 22:08:54 -07:00
parent c0f067c3cf
commit dda7a8c5f3
1 changed files with 2 additions and 1 deletions
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3
litex/soc/doc/csr.py
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@ -266,7 +266,8 @@ class DocumentedCSRRegion:
print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream) print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream)
if reg.size != self.csr_data_width: if reg.size != self.csr_data_width:
print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream) print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream)
print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1 }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1}", file=stream) lanes = self.busword / 8
print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + " }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + "}", file=stream)
print(" }", file=stream) print(" }", file=stream)
print("", file=stream) print("", file=stream)