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Sync ROM_BOOT_ADDRESS with main_ram location

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Rocket and Blackparrot main_ram starts at 0x80000000
Vexriscv main_ram starts at 0x40000000
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developandplay 2021-06-09 03:36:32 +02:00 committed by GitHub
parent bd1463514b
commit e0352a1f0f
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2
litex/tools/litex_sim.py
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@ -430,7 +430,7 @@ def main():
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))