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cpu/rocket: Add initial dcache/icache/dtlb/itlb configs for .dts generation. 

Hardwired and probably incorrect, will need to be checked/fixed.
This commit is contained in:
Florent Kermarrec 2023-02-20 10:47:09 +01:00
parent f2b0bf91eb
commit e15e115170
1 changed files with 16 additions and 0 deletions
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16
litex/soc/cores/cpu/rocket/core.py
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@ -369,6 +369,22 @@ class Rocket(CPU):
soc.add_config("CPU_COUNT", num_cores) soc.add_config("CPU_COUNT", num_cores)
soc.add_config("CPU_ISA", self.get_arch(self.variant)) soc.add_config("CPU_ISA", self.get_arch(self.variant))
# Constants for Cache so we can add them in the DTS.
soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_WAYS", 2) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_SIZE", 4096) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_WAYS", 2) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired?
# Constants for TLB so we can add them in the DTS.
soc.add_config("CPU_DTLB_SIZE", 4) # CHECKME: correct/hardwired?
soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_SIZE", 4) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired?
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "reset_address") assert hasattr(self, "reset_address")
self.specials += Instance("ExampleRocketSystem", **self.cpu_params) self.specials += Instance("ExampleRocketSystem", **self.cpu_params)