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cpu/vexriscv: Review/Cleanup #1022. 

Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
This commit is contained in:
Florent Kermarrec 2021-09-07 09:04:47 +02:00
parent 6b792dce54
commit e257d91d46
2 changed files with 20 additions and 12 deletions
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24
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -135,6 +135,7 @@ class VexRiscv(CPU, AutoCSR):
# # # # # #
# CPU Instance.
self.cpu_params = dict( self.cpu_params = dict(
i_clk = ClockSignal("sys"), i_clk = ClockSignal("sys"),
i_reset = ResetSignal("sys") | self.reset, i_reset = ResetSignal("sys") | self.reset,
@ -168,9 +169,11 @@ class VexRiscv(CPU, AutoCSR):
i_dBusWishbone_ERR = dbus.err i_dBusWishbone_ERR = dbus.err
) )
# Add Timer (Optional).
if with_timer: if with_timer:
self.add_timer() self.add_timer()
# Add Debug (Optional).
if "debug" in variant: if "debug" in variant:
self.add_debug() self.add_debug()
@ -332,15 +335,24 @@ class VexRiscv(CPU, AutoCSR):
platform.add_source(os.path.join(vdir, cpu_filename)) platform.add_source(os.path.join(vdir, cpu_filename))
def add_soc_components(self, soc, soc_region_cls): def add_soc_components(self, soc, soc_region_cls):
# Connect Debug interface to SoC.
if "debug" in self.variant: if "debug" in self.variant:
soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls( soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=
origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False)) soc_region_cls(
origin = soc.mem_map.get("vexriscv_debug"),
size = 0x100,
cached = False
)
)
# Pass I/D Caches info to software.
base_variant = str(self.variant.split('+')[0]) base_variant = str(self.variant.split('+')[0])
if base_variant == "lite" or base_variant == "minimal": # DCACHE is present on all variants except minimal and lite.
soc.add_config("CPU_NO_DCACHE") if not base_variant in ["minimal", "lite"]:
if base_variant == "minimal": soc.add_config("CPU_HAS_DCACHE")
soc.add_config("CPU_NO_ICACHE") # ICACHE is present on all variants except minimal.
if not base_variant in ["minimal"]:
soc.add_config("CPU_HAS_ICACHE")
def use_external_variant(self, variant_filename): def use_external_variant(self, variant_filename):
self.external_variant = True self.external_variant = True

8
litex/soc/cores/cpu/vexriscv/system.h
View File

@ -11,9 +11,7 @@ extern "C" {
__attribute__((unused)) static void flush_cpu_icache(void) __attribute__((unused)) static void flush_cpu_icache(void)
{ {
#if defined(CONFIG_CPU_NO_ICACHE) #if defined(CONFIG_CPU_HAS_ICACHE)
/* No instruction cache */
#else
asm volatile( asm volatile(
".word(0x100F)\n" ".word(0x100F)\n"
"nop\n" "nop\n"
@ -27,9 +25,7 @@ __attribute__((unused)) static void flush_cpu_icache(void)
__attribute__((unused)) static void flush_cpu_dcache(void) __attribute__((unused)) static void flush_cpu_dcache(void)
{ {
#if defined(CONFIG_CPU_NO_DCACHE) #if defined(CONFIG_CPU_HAS_DCACHE)
/* No data cache */
#else
asm volatile(".word(0x500F)\n"); asm volatile(".word(0x500F)\n");
#endif #endif
} }