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cpu: vexriscv: allow cpu_reset_address to be overridden 

Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-04-19 13:04:57 +08:00
parent 2ebfab5e1f
commit e2cf45b8a9
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/cpu/vexriscv/core.py
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@ -21,6 +21,7 @@ class VexRiscv(Module, AutoCSR):
self.reset = Signal() self.reset = Signal()
self.ibus = ibus = wishbone.Interface() self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface() self.dbus = dbus = wishbone.Interface()
self.cpu_reset_address = cpu_reset_address
self.interrupt = Signal(32) self.interrupt = Signal(32)
@ -28,7 +29,7 @@ class VexRiscv(Module, AutoCSR):
i_clk=ClockSignal(), i_clk=ClockSignal(),
i_reset=ResetSignal() | self.reset, i_reset=ResetSignal() | self.reset,
i_externalResetVector=cpu_reset_address, i_externalResetVector=self.cpu_reset_address,
i_externalInterruptArray=self.interrupt, i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0, i_timerInterrupt=0,