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Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert 

Revert LitexModule for AXILiteSRAM as well.
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enjoy-digital 2024-05-07 15:10:55 +02:00 committed by GitHub
parent 86a43c9ff7 26f5e8a149
commit e4cfe87109
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GPG Key ID: B5690EEEBB952194
1 changed files with 2 additions and 2 deletions
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4
litex/soc/interconnect/axi/axi_lite.py
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@ -218,7 +218,7 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
# AXI-Lite SRAM ------------------------------------------------------------------------------------
class AXILiteSRAM(LiteXModule):
class AXILiteSRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None, name=None):
if bus is None:
bus = AXILiteInterface()
@ -257,7 +257,7 @@ class AXILiteSRAM(LiteXModule):
port_dat_r = port.dat_r,
port_dat_w = port.dat_w if not read_only else None,
port_we = port.we if not read_only else None)
self.fsm = fsm
self.submodules.fsm = fsm
self.comb += comb
# AXI-Lite Data-Width Converter --------------------------------------------------------------------