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cva6: Fix reset integration 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-03-15 16:14:09 +01:00
parent 3ae3d66c80
commit e50b5d0d45
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/cva6/core.py
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@ -54,7 +54,7 @@ def add_manifest_sources(platform, manifest):
platform.add_verilog_include_path(os.path.join(basedir, res.group(2))) platform.add_verilog_include_path(os.path.join(basedir, res.group(2)))
else: else:
filename = res.group(2) filename = res.group(2)
if isinstance(platform, XilinxPlatform): # TODO: other FPGAs if True: # TODO: other FPGAs
if filename.endswith("tc_sram_wrapper.sv"): if filename.endswith("tc_sram_wrapper.sv"):
filename = filename.replace("tc_sram_wrapper.sv", "tc_sram_fpga_wrapper.sv") filename = filename.replace("tc_sram_wrapper.sv", "tc_sram_fpga_wrapper.sv")
platform.add_source(os.path.join(basedir, "common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv")) platform.add_source(os.path.join(basedir, "common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv"))
@ -119,7 +119,7 @@ class CVA6(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk_i = ClockSignal("sys"), i_clk_i = ClockSignal("sys"),
i_rst_n = ~ResetSignal("sys") | self.reset, i_rst_n = ~ResetSignal("sys") & ~self.reset,
# Interrupts # Interrupts
i_irq_sources = self.interrupt, i_irq_sources = self.interrupt,