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uart: minor cleanup and fix

This commit is contained in:
Sebastien Bourdeauducq 2014-10-10 15:33:27 +08:00
parent 5e5f436aa6
commit e53fb88b85
1 changed files with 2 additions and 3 deletions
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5
misoclib/uart/__init__.py
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@ -125,7 +125,7 @@ class UART(Module, AutoCSR):
self.tx.sink.stb.eq(0) self.tx.sink.stb.eq(0)
), ),
If(self.rx.source.stb, If(self.rx.source.stb,
self._r_rxtx.w.eq(self.rx.source.d) self._r_rxtx.w.eq(self.rx.source.payload.d)
) )
] ]
self.comb += [ self.comb += [
@ -135,9 +135,8 @@ class UART(Module, AutoCSR):
class UARTTB(Module): class UARTTB(Module):
def __init__(self): def __init__(self):
MHz=1000000
self.clk_freq = 83333333 self.clk_freq = 83333333
self.baud = 3*MHz self.baud = 3000000
self.pads = Record([("rx", 1), ("tx", 1)]) self.pads = Record([("rx", 1), ("tx", 1)])
self.submodules.slave = UART(self.pads, self.clk_freq, self.baud) self.submodules.slave = UART(self.pads, self.clk_freq, self.baud)