Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset. 

It seems EHXPLLL does not loose locked when reseted.
This commit is contained in:
Florent Kermarrec 2020-11-26 18:54:38 +01:00
parent b02753ecfa
commit e5a7375b30
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/cores/clock/lattice_ecp5.py
View File

@ -90,6 +90,7 @@ class ECP5PLL(Module):
def do_finalize(self): def do_finalize(self):
config = self.compute_config() config = self.compute_config()
clkfb = Signal() clkfb = Signal()
locked = Signal()
self.params.update( self.params.update(
attr=[ attr=[
("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)), ("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)),
@ -99,7 +100,7 @@ class ECP5PLL(Module):
("MFG_GMCREF_SEL", "2")], ("MFG_GMCREF_SEL", "2")],
i_RST = self.reset, i_RST = self.reset,
i_CLKI = self.clkin, i_CLKI = self.clkin,
o_LOCK = self.locked, o_LOCK = locked,
p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1. p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
p_CLKOS3_ENABLE = "ENABLED", p_CLKOS3_ENABLE = "ENABLED",
p_CLKOS3_DIV = 1, p_CLKOS3_DIV = 1,
@ -108,6 +109,7 @@ class ECP5PLL(Module):
p_CLKFB_DIV = config["clkfb_div"], p_CLKFB_DIV = config["clkfb_div"],
p_CLKI_DIV = config["clki_div"], p_CLKI_DIV = config["clki_div"],
) )
self.comb += self.locked.eq(locked & ~self.reset)
for n, (clk, f, p, m) in sorted(self.clkouts.items()): for n, (clk, f, p, m) in sorted(self.clkouts.items()):
n_to_l = {0: "P", 1: "S", 2: "S2"} n_to_l = {0: "P", 1: "S", 2: "S2"}
div = config["clko{}_div".format(n)] div = config["clko{}_div".format(n)]