soc/interconnect/wishbone: add FlipFlop (should be removed)

This commit is contained in:
Florent Kermarrec 2016-04-25 19:14:20 +02:00
parent b6d8999471
commit e6681bbb9c
1 changed files with 7 additions and 0 deletions

View File

@ -10,6 +10,13 @@ from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import csr
# TODO: rewrite without FlipFlop and Counter
@ResetInserter()
@CEInserter()
class FlipFlop(Module):
def __init__(self, *args, **kwargs):
self.d = Signal(*args, **kwargs)
self.q = Signal(*args, **kwargs)
self.sync += self.q.eq(self.d)
_layout = [