cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility.

This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards.
This commit is contained in:
Florent Kermarrec 2022-03-17 16:00:05 +01:00
parent 2ec0ebe40f
commit e6e3a909f2
2 changed files with 5 additions and 0 deletions

View File

@ -254,6 +254,7 @@ class NaxRiscv(CPU):
platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls):
# Set UART/Timer0 CSRs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)

View File

@ -375,6 +375,10 @@ class VexRiscvSMP(CPU):
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls):
# Set UART/Timer0 CSRs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())