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targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 

Now supported by Trellis/Nextpnr.
This commit is contained in:
Florent Kermarrec 2019-03-04 09:27:31 +01:00
parent 5ef28bdf75
commit e6f97e08d2
1 changed files with 2 additions and 5 deletions
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7
litex/boards/targets/ulx3s.py
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@ -26,6 +26,7 @@ class _CRG(Module):
# clk / rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
platform.add_period_constraint(clk25, 40.0)
# pll
self.submodules.pll = pll = ECP5PLL()
@ -33,11 +34,7 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, 50e6, phase=11)
pll.create_clkout(self.cd_sys_ps, 50e6, phase=20)
# FIXME: AsyncResetSynchronizer needs FD1S3BX support.
#self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
self.comb += self.cd_sys.rst.eq(rst)
platform.add_period_constraint(self.cd_sys.clk, 20.0)
platform.add_period_constraint(self.cd_sys_ps.clk, 20.0)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
# sdram clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)