liblitedram/bist: small refactor of bist functions
`SDRAM_TEST_DATA_BYTES` definition was incorrect as it treated size specified in CSR subregisters as if it was a byte count. Correct way to calculate that is to use definitions from `sdram_phy.h`. ``` #define SDRAM_TEST_DATA_BYTES (SDRAM_PHY_DFI_DATABITS / 8 * SDRAM_PHY_PHASES) ``` Also: - extracted code to `sdram_bist_[write|read]` functions - made global variables static - fixed formatting Signed-off-by: Michal Sieron <msieron@antmicro.com>
This commit is contained in:
Michal Sieron
parent
eb688d3af7
commit
e7e1b16027
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@ -5,31 +5,21 @@
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#if defined(CSR_SDRAM_GENERATOR_BASE) && defined(CSR_SDRAM_CHECKER_BASE)
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <uart.h>
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#include <time.h>
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#include <console.h>
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#include <liblitedram/bist.h>
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#include <generated/sdram_phy.h>
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#define SDRAM_TEST_BASE 0x00000000
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#define SDRAM_TEST_DATA_BYTES (CSR_SDRAM_DFII_PI0_RDDATA_SIZE*4)
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#define SDRAM_TEST_DATA_BYTES (SDRAM_PHY_DFI_DATABITS / 8 * SDRAM_PHY_PHASES)
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uint32_t wr_ticks;
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uint32_t wr_length;
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uint32_t rd_ticks;
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uint32_t rd_length;
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uint32_t rd_errors;
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__attribute__((unused)) static void cdelay(int i)
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{
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#ifndef CONFIG_BIOS_NO_DELAYS
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while(i > 0) {
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__asm__ volatile(CONFIG_CPU_NOP);
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i--;
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}
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#endif
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}
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static uint32_t wr_ticks = 0;
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static uint32_t wr_length = 0;
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static uint32_t rd_ticks = 0;
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static uint32_t rd_length = 0;
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static uint32_t rd_errors = 0;
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static uint32_t pseudo_random_bases[128] = {
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0x000e4018,0x0003338d,0x00233429,0x001f589d,
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@ -66,65 +56,59 @@ static uint32_t pseudo_random_bases[128] = {
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0x00027e36,0x000e51ae,0x002e7627,0x00275c9f,
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};
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void sdram_bist_loop(uint32_t loop, uint32_t burst_length, uint32_t random) {
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static void sdram_bist_write(uint32_t base, uint32_t length) {
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/* Prepare write */
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sdram_generator_reset_write(1);
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sdram_generator_random_write(1); /* Random data */
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sdram_generator_base_write(base);
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sdram_generator_end_write(base + length);
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sdram_generator_length_write(length);
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/* Start write */
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sdram_generator_start_write(1);
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/* Wait write */
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while(sdram_generator_done_read() == 0);
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}
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static void sdram_bist_read(uint32_t base, uint32_t length) {
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/* Prepare read */
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sdram_checker_reset_write(1);
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sdram_checker_random_write(1); /* Random data */
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sdram_checker_base_write(base);
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sdram_checker_end_write(base + length);
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sdram_checker_length_write(length);
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/* Start read */
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sdram_checker_start_write(1);
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/* Wait read */
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while(sdram_checker_done_read() == 0);
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}
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static void sdram_bist_loop(uint32_t loop, uint32_t burst_length, uint32_t random) {
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int i;
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uint32_t base;
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uint32_t length;
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length = burst_length*SDRAM_TEST_DATA_BYTES;
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length = burst_length * SDRAM_TEST_DATA_BYTES;
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rd_errors = 0;
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for(i=0; i<128; i++) {
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for (i = 0; i < 128; i++) {
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if (random)
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base = SDRAM_TEST_BASE + pseudo_random_bases[(i+loop)%128]*SDRAM_TEST_DATA_BYTES;
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else
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base = SDRAM_TEST_BASE + ((i+loop)%128)*SDRAM_TEST_DATA_BYTES;
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if (i == 0) {
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/* Prepare first write */
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sdram_generator_reset_write(1);
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sdram_generator_reset_write(0);
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sdram_generator_random_write(1); /* Random data */
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sdram_generator_base_write(base);
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sdram_generator_end_write(base + length);
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sdram_generator_length_write(length);
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cdelay(100);
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}
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/* Start write */
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sdram_generator_start_write(1);
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/* Prepare next read */
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sdram_checker_reset_write(1);
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sdram_checker_reset_write(0);
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sdram_checker_random_write(1); /* Random data */
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sdram_checker_base_write(base);
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sdram_checker_end_write(base + length);
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sdram_checker_length_write(length);
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cdelay(100);
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/* Wait write */
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while(sdram_generator_done_read() == 0);
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sdram_bist_write(base, length);
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/* Get write results */
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wr_length += length;
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wr_ticks += sdram_generator_ticks_read();
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/* Start read */
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sdram_checker_start_write(1);
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if (i != 127) {
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if (random)
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base = SDRAM_TEST_BASE + pseudo_random_bases[(i+1+loop)%128]*SDRAM_TEST_DATA_BYTES;
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else
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base = SDRAM_TEST_BASE + ((i+1+loop)%128)*SDRAM_TEST_DATA_BYTES;
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/* Prepare next write */
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sdram_generator_reset_write(1);
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sdram_generator_reset_write(0);
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sdram_generator_random_write(1); /* Random data */
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sdram_generator_base_write(base);
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sdram_generator_end_write(base + length);
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sdram_generator_length_write(length);
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cdelay(100);
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}
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/* Wait read */
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while(sdram_checker_done_read() == 0);
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sdram_bist_read(base, length);
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/* Get read results */
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rd_length += length;
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rd_ticks += sdram_checker_ticks_read();
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rd_errors += sdram_checker_errors_read();
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rd_length += length;
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}
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}
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@ -138,19 +122,14 @@ static uint32_t compute_speed_mibs(uint32_t length, uint32_t ticks) {
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void sdram_bist(uint32_t burst_length, uint32_t random)
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{
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uint32_t i;
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uint32_t total_length;
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uint64_t total_length;
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uint32_t total_errors;
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printf("Starting SDRAM BIST with burst_length=%d and random=%d\n", burst_length, random);
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printf("Starting SDRAM BIST with burst_length=%lu and random=%lu\n", burst_length, random);
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i = 0;
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total_length = 0;
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total_errors = 0;
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for(;;) {
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/* Exit on key pressed */
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if (readchar_nonblock())
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break;
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for (i = 0; !readchar_nonblock(); i++) { /* Exit on key pressed */
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/* Bist loop */
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sdram_bist_loop(i, burst_length, random);
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@ -159,11 +138,12 @@ void sdram_bist(uint32_t burst_length, uint32_t random)
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printf("WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS\n");
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}
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if (i%100 == 100-1) {
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printf("%15u %15u %12u %12u\n",
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compute_speed_mibs(wr_length, wr_ticks),
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compute_speed_mibs(rd_length, rd_ticks),
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total_length/(1024*1024),
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total_errors);
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printf("%15lu %15lu %12llu %12lu\n",
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compute_speed_mibs(wr_length, wr_ticks),
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compute_speed_mibs(rd_length, rd_ticks),
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total_length/(1024*1024),
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total_errors);
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total_length += wr_length;
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total_errors += rd_errors;
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@ -174,7 +154,6 @@ void sdram_bist(uint32_t burst_length, uint32_t random)
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rd_ticks = 0;
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rd_errors = 0;
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}
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i++;
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}
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}
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@ -4,7 +4,7 @@
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#ifndef __SDRAM_BIST_H
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#define __SDRAM_BIST_H
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void sdram_bist_loop(uint32_t loop, uint32_t burst_length, uint32_t random);
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#include <stdint.h>
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void sdram_bist(uint32_t burst_length, uint32_t random);
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#endif /* __SDRAM_BIST_H */
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