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tools/litex_sim: allow to enable BIST modules 

Signed-off-by: Michal Sieron <msieron@antmicro.com>
This commit is contained in:
Michal Sieron 2023-01-09 16:44:33 +01:00
parent c834387965
commit eb688d3af7
1 changed files with 5 additions and 1 deletions
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6
litex/tools/litex_sim.py
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@ -149,6 +149,7 @@ class SimSoC(SoCCore):
sdram_data_width = 32,
sdram_spd_data = None,
sdram_verbosity = 0,
with_bist = False,
with_i2c = False,
with_sdcard = False,
with_spi_flash = False,
@ -195,7 +196,8 @@ class SimSoC(SoCCore):
module = sdram_module,
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False
l2_cache_reverse = False,
with_bist = with_bist
)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
@ -373,6 +375,7 @@ def sim_args(parser):
parser.add_argument("--sdram-init", default=None, help="SDRAM init file (.bin or .json).")
parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump.")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity.")
parser.add_argument("--with-bist", action="store_true", help="Enable SDRAM BIST modules.")
# Ethernet /Etherbone.
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
@ -476,6 +479,7 @@ def main():
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(
with_sdram = args.with_sdram,
with_bist = args.with_bist,
with_ethernet = args.with_ethernet,
ethernet_phy_model = args.ethernet_phy_model,
with_etherbone = args.with_etherbone,