Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

build: pass build_name to get_verilog (same name for top module and top level file)

This commit is contained in:
Florent Kermarrec 2015-12-02 14:18:09 +01:00
parent b7a1888a36
commit e8262ed447
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/build/altera/quartus.py
View File

@ -113,7 +113,7 @@ quartus_sta {build_name} -c {build_name}
class AlteraQuartusToolchain: class AlteraQuartusToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path="/opt/Altera", run=True): toolchain_path="/opt/Altera", run=True, **kwargs):
cwd = os.getcwd() cwd = os.getcwd()
tools.mkdir_noerror(build_dir) tools.mkdir_noerror(build_dir)
os.chdir(build_dir) os.chdir(build_dir)
@ -122,7 +122,7 @@ class AlteraQuartusToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)

4
litex/build/lattice/diamond.py
View File

@ -76,7 +76,7 @@ def _run_diamond(build_name, source, ver=None):
class LatticeDiamondToolchain: class LatticeDiamondToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path="/opt/Diamond", run=True): toolchain_path="/opt/Diamond", run=True, **kwargs):
tools.mkdir_noerror(build_dir) tools.mkdir_noerror(build_dir)
cwd = os.getcwd() cwd = os.getcwd()
os.chdir(build_dir) os.chdir(build_dir)
@ -85,7 +85,7 @@ class LatticeDiamondToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)

4
litex/build/xilinx/ise.py
View File

@ -133,7 +133,7 @@ class XilinxISEToolchain:
self.ise_commands = "" self.ise_commands = ""
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path=None, source=None, run=True, mode="xst"): toolchain_path=None, source=None, run=True, mode="xst", **kwargs):
if not isinstance(fragment, _Fragment): if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
if toolchain_path is None: if toolchain_path is None:
@ -155,7 +155,7 @@ class XilinxISEToolchain:
os.chdir(build_dir) os.chdir(build_dir)
try: try:
if mode == "xst" or mode == "yosys": if mode == "xst" or mode == "yosys":
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
vns = v_output.ns vns = v_output.ns
named_sc, named_pc = platform.resolve_signals(vns) named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v" v_file = build_name + ".v"

4
litex/build/xilinx/vivado.py
View File

@ -112,7 +112,7 @@ class XilinxVivadoToolchain:
tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path="/opt/Xilinx/Vivado", source=True, run=True): toolchain_path="/opt/Xilinx/Vivado", source=True, run=True, **kwargs):
tools.mkdir_noerror(build_dir) tools.mkdir_noerror(build_dir)
cwd = os.getcwd() cwd = os.getcwd()
os.chdir(build_dir) os.chdir(build_dir)
@ -120,7 +120,7 @@ class XilinxVivadoToolchain:
if not isinstance(fragment, _Fragment): if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)